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[Qemu-commits] [qemu/qemu] 594196: target/xtensa: get rid of centralized

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 594196: target/xtensa: get rid of centralized SR properties
Date: Tue, 21 May 2019 03:47:46 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 59419607fb340b776543f52970aefcb784eb046e
      
https://github.com/qemu/qemu/commit/59419607fb340b776543f52970aefcb784eb046e
  Author: Max Filippov <address@hidden>
  Date:   2019-05-10 (Fri, 10 May 2019)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: get rid of centralized SR properties

SR numbers are not unique: different Xtensa options may reuse SR number
for different purposes. Introduce generic rsr/wsr functions and xsr
template and use them instead of centralized SR access functions. Change
prototypes of specific rsr/wsr functions to match XtensaOpcodeOp and use
them instead of centralized SR access functions. Put xtensa option that
introduces SR into the second opcode description parameter and use it to
test for rsr/wsr/xsr opcode validity. Extract SR and UR names for the
xtensa_cpu_dump_state from libisa. Merge SRs and URs in the dump.
Register names of used SR/UR in init_libisa and use these names for TCG
globals referencing these SR/UR.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 5f7f36d07e0e3178987d6d7711e36f532380b38e
      
https://github.com/qemu/qemu/commit/5f7f36d07e0e3178987d6d7711e36f532380b38e
  Author: Max Filippov <address@hidden>
  Date:   2019-05-10 (Fri, 10 May 2019)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/mmu_helper.c

  Log Message:
  -----------
  target/xtensa: make internal MMU functions static

Remove declarations of the internal mmu_helper functions from the cpu.h,
make these functions static and shuffle them.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 944bb3320aeea6285d495b645f4700c3a20668e8
      
https://github.com/qemu/qemu/commit/944bb3320aeea6285d495b645f4700c3a20668e8
  Author: Max Filippov <address@hidden>
  Date:   2019-05-10 (Fri, 10 May 2019)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/overlay_tool.h

  Log Message:
  -----------
  target/xtensa: define IDMA and gather/scatter IRQ types

IDMA and scatter/gather features introduced new IRQ types that
overlay_tool.h need to initialize Xtensa configuration.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 631a77a03bc8905790af6fe3fd44c6c7ff285c73
      
https://github.com/qemu/qemu/commit/631a77a03bc8905790af6fe3fd44c6c7ff285c73
  Author: Max Filippov <address@hidden>
  Date:   2019-05-10 (Fri, 10 May 2019)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: add parity/ECC option SRs

Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option.
The implementation is trivial since we don't emulate parity/ECC yet.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 4d04ea35b30f9ba4097b746622eea07be3f2c363
      
https://github.com/qemu/qemu/commit/4d04ea35b30f9ba4097b746622eea07be3f2c363
  Author: Max Filippov <address@hidden>
  Date:   2019-05-10 (Fri, 10 May 2019)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/helper.h
    M target/xtensa/mmu_helper.c
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: implement MPU option

The Memory Protection Unit Option (MPU) is a combined instruction and
data memory protection unit with more protection flexibility than the
Region Protection Option or the Region Translation Option but without
any translation capability. It does no demand paging and does not
reference a memory-based page table.

Add memory protection unit option, internal state, SRs and opcodes.
Implement MPU entries dumping in dump_mmu.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 75eed0e5f74a05ade59b874aff3b652b5ee2e47e
      
https://github.com/qemu/qemu/commit/75eed0e5f74a05ade59b874aff3b652b5ee2e47e
  Author: Max Filippov <address@hidden>
  Date:   2019-05-14 (Tue, 14 May 2019)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: implement DIWBUI.P opcode

This is a recent addition to the set of data cache opcodes.

Signed-off-by: Max Filippov <address@hidden>


  Commit: c884400f2988b1f016e331e406ef9102c60d6722
      
https://github.com/qemu/qemu/commit/c884400f2988b1f016e331e406ef9102c60d6722
  Author: Max Filippov <address@hidden>
  Date:   2019-05-15 (Wed, 15 May 2019)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: implement block prefetch option opcodes

Block prefetch option adds a bunch of non-privileged opcodes that may be
implemented as nops since QEMU doesn't model caches.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Max Filippov <address@hidden>


  Commit: 98736654f3dfbf984d9e26c9be0480b0560c1067
      
https://github.com/qemu/qemu/commit/98736654f3dfbf984d9e26c9be0480b0560c1067
  Author: Max Filippov <address@hidden>
  Date:   2019-05-15 (Wed, 15 May 2019)

  Changed paths:
    M target/xtensa/cpu.h

  Log Message:
  -----------
  target/xtensa: update list of exception causes

Add XEA2 exception cause codes defined in recent Xtensa ISA releases.

Signed-off-by: Max Filippov <address@hidden>


  Commit: b345e140534ea17814b02bdf8798f18db6295304
      
https://github.com/qemu/qemu/commit/b345e140534ea17814b02bdf8798f18db6295304
  Author: Max Filippov <address@hidden>
  Date:   2019-05-15 (Wed, 15 May 2019)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c
    A tests/tcg/xtensa/test_exclusive.S

  Log Message:
  -----------
  target/xtensa: implement exclusive access option

The Exclusive Instructions provide a general-purpose mechanism for
atomic updates of memory-based synchronization variables that can be
used for exclusion algorithms.

Use cmpxchg-based implementation that is sufficient for the typical use
of exclusive access in atomic operations.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 293c76cb48332d2bbd70bd975dc60ee3650b3170
      
https://github.com/qemu/qemu/commit/293c76cb48332d2bbd70bd975dc60ee3650b3170
  Author: Peter Maydell <address@hidden>
  Date:   2019-05-21 (Tue, 21 May 2019)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/helper.c
    M target/xtensa/helper.h
    M target/xtensa/mmu_helper.c
    M target/xtensa/op_helper.c
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c
    A tests/tcg/xtensa/test_exclusive.S

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into 
staging

target/xtensa: SR reorganization and options for modern cores

Reorganize special register handling to support configurations with
conflicting SR definitions.

Implement options used by the modern xtensa cores:
- memory protection unit;
- block prefetch;
- exclusive access

Add special register definitions and IRQ types for ECC/parity,
gather/scatter and IDMA.

# gpg: Signature made Mon 20 May 2019 18:53:05 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Max Filippov <address@hidden>" [unknown]
# gpg:                 aka "Max Filippov <address@hidden>" [full]
# gpg:                 aka "Max Filippov <address@hidden>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190520-xtensa:
  target/xtensa: implement exclusive access option
  target/xtensa: update list of exception causes
  target/xtensa: implement block prefetch option opcodes
  target/xtensa: implement DIWBUI.P opcode
  target/xtensa: implement MPU option
  target/xtensa: add parity/ECC option SRs
  target/xtensa: define IDMA and gather/scatter IRQ types
  target/xtensa: make internal MMU functions static
  target/xtensa: get rid of centralized SR properties

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/2259637b95be...293c76cb4833
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