[Qemu-commits] [qemu/qemu] 62c7ec: target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 62c7ec3488fe0dcbabffd543f458914e27736115
      
https://github.com/qemu/qemu/commit/62c7ec3488fe0dcbabffd543f458914e27736115
  Author: Aaron Lindsay OS <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

This bug was introduced in:
    commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
    target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Signed-off-by: Aaron Lindsay <address@hidden>
Reported-by: Laurent Desnogues <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 831a2fca343ebcd6651eab9102bd7a36b77da65d
      
https://github.com/qemu/qemu/commit/831a2fca343ebcd6651eab9102bd7a36b77da65d
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement HACR_EL2

HACR_EL2 is a register with IMPDEF behaviour, which allows
implementation specific trapping to EL2. Implement it as RAZ/WI,
since QEMU's implementation has no extra traps. This also
matches what h/w implementations like Cortex-A53 and A57 do.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: abd5abc58c5d4c9bd23427b0998a44eb87ed47a2
      
https://github.com/qemu/qemu/commit/abd5abc58c5d4c9bd23427b0998a44eb87ed47a2
  Author: Catherine Ho <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper-a64.c

  Log Message:
  -----------
  target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be

The lo,hi order is different from the comments. And in commit
1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128"), it changes
the original code logic. So just restore the old code logic before this
commit:
do_paired_cmpxchg64_be():
    cmpv = int128_make128(env->exclusive_high, env->exclusive_val);
    newv = int128_make128(new_hi, new_lo);

This fixes a bug that would only be visible for big-endian
AArch64 guest code.

Fixes: 1ec182c33379 ("target/arm: Convert to HAVE_CMPXCHG128")
Signed-off-by: Catherine Ho <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: added note that bug only affects BE guests]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b5bd7440422bb66deaceb812bb9287a6a3cdf10c
      
https://github.com/qemu/qemu/commit/b5bd7440422bb66deaceb812bb9287a6a3cdf10c
  Author: Alex Bennée <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: relax permission checks for HWCAP_CPUID registers

Although technically not visible to userspace the kernel does make
them visible via a trap and emulate ABI. We provide a new permission
mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust
the minimum permission check accordingly.

Signed-off-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6c5c0fec29bbfe36c64eca1edfd8455be46b77c6
      
https://github.com/qemu/qemu/commit/6c5c0fec29bbfe36c64eca1edfd8455be46b77c6
  Author: Alex Bennée <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: expose CPUID registers to userspace

A number of CPUID registers are exposed to userspace by modern Linux
kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's
user-mode emulation we don't need to emulate the kernels trap but just
return the value the trap would have done. To avoid too much #ifdef
hackery we process ARMCPRegInfo with a new helper (modify_arm_cp_regs)
before defining the registers. The modify routine is driven by a
simple data structure which describes which bits are exported and
which are fixed.

Signed-off-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 522641660c3de64ed8322b8636c58625cd564a3f
      
https://github.com/qemu/qemu/commit/522641660c3de64ed8322b8636c58625cd564a3f
  Author: Alex Bennée <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: expose MPIDR_EL1 to userspace

As this is a single register we could expose it with a simple ifdef
but we use the existing modify_arm_cp_regs mechanism for consistency.

Signed-off-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d040242effe47850060d2ef1c461ff637d88a84d
      
https://github.com/qemu/qemu/commit/d040242effe47850060d2ef1c461ff637d88a84d
  Author: Alex Bennée <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: expose remaining CPUID registers as RAZ

There are a whole bunch more registers in the CPUID space which are
currently not used but are exposed as RAZ. To avoid too much
duplication we expand ARMCPRegUserSpaceInfo to understand glob
patterns so we only need one entry to tweak whole ranges of registers.

Signed-off-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 37020ff1539800b367fd69c1386e0d841f48b1ed
      
https://github.com/qemu/qemu/commit/37020ff1539800b367fd69c1386e0d841f48b1ed
  Author: Alex Bennée <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user/elfload: enable HWCAP_CPUID for AArch64

Userspace programs should (in theory) query the ELF HWCAP before
probing these registers. Now we have implemented them all make it
public.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 823e1b3818f9b10b824ddcd756983b6e2fa68730
      
https://github.com/qemu/qemu/commit/823e1b3818f9b10b824ddcd756983b6e2fa68730
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/machine.c

  Log Message:
  -----------
  arm: Allow system registers for KVM guests to be changed by QEMU code

At the moment the Arm implementations of kvm_arch_{get,put}_registers()
don't support having QEMU change the values of system registers
(aka coprocessor registers for AArch32). This is because although
kvm_arch_get_registers() calls write_list_to_cpustate() to
update the CPU state struct fields (so QEMU code can read the
values in the usual way), kvm_arch_put_registers() does not
call write_cpustate_to_list(), meaning that any changes to
the CPU state struct fields will not be passed back to KVM.

The rationale for this design is documented in a comment in the
AArch32 kvm_arch_put_registers() -- writing the values in the
cpregs list into the CPU state struct is "lossy" because the
write of a register might not succeed, and so if we blindly
copy the CPU state values back again we will incorrectly
change register values for the guest. The assumption was that
no QEMU code would need to write to the registers.

However, when we implemented debug support for KVM guests, we
broke that assumption: the code to handle "set the guest up
to take a breakpoint exception" does so by updating various
guest registers including ESR_EL1.

Support this by making kvm_arch_put_registers() synchronize
CPU state back into the list. We sync only those registers
where the initial write succeeds, which should be sufficient.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Tested-by: Dongjiu Geng <address@hidden>


  Commit: 6ea564872238a25de2bdac8a61c485df6bcce9d6
      
https://github.com/qemu/qemu/commit/6ea564872238a25de2bdac8a61c485df6bcce9d6
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Remove Peter Crosthwaite from various entries

Peter Crosthwaite hasn't had the bandwidth to do code review or
other QEMU work for some time now -- remove his email address
from MAINTAINERS file entries so we don't bombard him with
patch emails.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 935fe442dc234c7b3fa52d346ced7a614696107e
      
https://github.com/qemu/qemu/commit/935fe442dc234c7b3fa52d346ced7a614696107e
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Allow byte accesses to SHPR1

The code for handling the NVIC SHPR1 register intends to permit
byte and halfword accesses (as the architecture requires). However
the 'case' line for it only lists the base address of the
register, so attempts to access bytes other than the first one
end up in the "bad write" default logic. This bug was added
accidentally when we split out the SHPR1 logic from SHPR2 and
SHPR3 to support v6M.

Fixes: 7c9140afd594 ("nvic: Handle ARMv6-M SCS reserved registers")
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
The Zephyr RTOS happens to access SHPR1 byte at a time,
which is how I spotted this.


  Commit: 5007c904e158aaaf97e65338e52f5ef9e8df0944
      
https://github.com/qemu/qemu/commit/5007c904e158aaaf97e65338e52f5ef9e8df0944
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c

  Log Message:
  -----------
  hw/arm/armsse: Fix miswiring of expansion IRQs

In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
the ARMSSE, we set up the wiring of the expansion IRQs via nested
loops: the outer loop on 'i' loops for each CPU, and the inner loop
on 'j' loops for each interrupt. Fix a typo which meant we were
wiring every expansion IRQ line to external IRQ 0 on CPU 0 and
to external IRQ 1 on CPU 1.

Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration")
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 2900847ff4c862887af750935a875059615f509a
      
https://github.com/qemu/qemu/commit/2900847ff4c862887af750935a875059615f509a
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-sve.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Rely on optimization within tcg_gen_gvec_or

Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.

Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 264d2a481a6c34dfda53be3fbea66116bcef9c5a
      
https://github.com/qemu/qemu/commit/264d2a481a6c34dfda53be3fbea66116bcef9c5a
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use vector minmax expanders for aarch64

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6f2782218230bbb33fa22f9a2f73f8a570046007
      
https://github.com/qemu/qemu/commit/6f2782218230bbb33fa22f9a2f73f8a570046007
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use vector minmax expanders for aarch32

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9ecd3c5c1651fa7f9adbedff4806a2da0b50490c
      
https://github.com/qemu/qemu/commit/9ecd3c5c1651fa7f9adbedff4806a2da0b50490c
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use tcg integer min/max primitives for neon

The 32-bit PMIN/PMAX has been decomposed to scalars,
and so can be trivially expanded inline.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a5c5dc53c4688efc149b235361d2d49869e77139
      
https://github.com/qemu/qemu/commit/a5c5dc53c4688efc149b235361d2d49869e77139
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon_helper.c

  Log Message:
  -----------
  target/arm: Remove neon min/max helpers

These are now unused.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b0a909a48a08cbba05d65af620ddd3aac29135ee
      
https://github.com/qemu/qemu/commit/b0a909a48a08cbba05d65af620ddd3aac29135ee
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix vfp_gdb_get/set_reg vs FPSCR

The components of this register is stored in several
different locations.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ec527e4eeccc31e3beadf3b61b66c61bbd873811
      
https://github.com/qemu/qemu/commit/ec527e4eeccc31e3beadf3b61b66c61bbd873811
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Fix arm_cpu_dump_state vs FPSCR

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 55a889456ef78f3f9b8eae9846c2f1453b1dd77b
      
https://github.com/qemu/qemu/commit/55a889456ef78f3f9b8eae9846c2f1453b1dd77b
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Split out flags setting from vfp compares

Minimize the code within a macro by splitting out a helper function.
Use deposit32 instead of manual bit manipulation.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 18aaa59c622208743565307668a2100ab24f7de9
      
https://github.com/qemu/qemu/commit/18aaa59c622208743565307668a2100ab24f7de9
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]

Given that we mask bits properly on set, there is no reason
to mask them again on get.  We failed to clear the exception
status bits, 0x9f, which means that the wrong value would be
returned on get.  Except in the (probably normal) case in which
the set clears all of the bits.

Simplify the code in set to also clear the RES0 bits.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a4d5846245c5e029e5aa3945a9bda1de1c3fedbf
      
https://github.com/qemu/qemu/commit/a4d5846245c5e029e5aa3945a9bda1de1c3fedbf
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/neon_helper.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Split out FPSCR.QC to a vector field

Change the representation of this field such that it is easy
to set from vector code.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 89e68b575e138d0af1435f11a8ffcd8779c237bd
      
https://github.com/qemu/qemu/commit/89e68b575e138d0af1435f11a8ffcd8779c237bd
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Use vector operations for saturation

For same-sign saturation, we have tcg vector operations.  We can
compute the QC bit by comparing the saturated value against the
unsaturated value.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d8efe78e8039511b95c23d75bb48eca6873fbb0f
      
https://github.com/qemu/qemu/commit/d8efe78e8039511b95c23d75bb48eca6873fbb0f
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Add missing clear_tail calls

Fortunately, the functions affected are so far only called from SVE,
so there is no tail to be cleared.  But as we convert more of AdvSIMD
to gvec, this will matter.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0f8b09b22234460cb5b8766a25066cf6b5f06842
      
https://github.com/qemu/qemu/commit/0f8b09b22234460cb5b8766a25066cf6b5f06842
  Author: Sandra Loosemore <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: Send a reply to the vKill packet.

Per the GDB remote protocol documentation

https://sourceware.org/gdb/current/onlinedocs/gdb/Packets.html#index-vKill-packet

the debug stub is expected to send a reply to the 'vKill' packet.  At
least some versions of GDB crash if the gdb stub simply exits without
sending a reply.  This patch fixes QEMU's gdb stub to conform to the
expected behavior.

Note that QEMU's existing handling of the legacy 'k' packet is
correct: in that case GDB does not expect a reply, and QEMU does not
send one.

Signed-off-by: Sandra Loosemore <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 81dbcfa9e1d8bab3f7c4cc923c0b40cd666f374f
      
https://github.com/qemu/qemu/commit/81dbcfa9e1d8bab3f7c4cc923c0b40cd666f374f
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-15 (Fri, 15 Feb 2019)

  Changed paths:
    M MAINTAINERS
    M gdbstub.c
    M hw/arm/armsse.c
    M hw/intc/armv7m_nvic.c
    M linux-user/elfload.c
    M target/arm/cpu.h
    M target/arm/helper-a64.c
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/machine.c
    M target/arm/neon_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-sve.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190215' 
into staging

target-arm queue:
 * gdbstub: Send a reply to the vKill packet
 * Improve codegen for neon min/max and saturating arithmetic
 * Fix a bug in clearing FPSCR exception status bits
 * hw/arm/armsse: Fix miswiring of expansion IRQs
 * hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
 * MAINTAINERS: Remove Peter Crosthwaite from various entries
 * arm: Allow system registers for KVM guests to be changed by QEMU code
 * linux-user: support HWCAP_CPUID which exposes ID registers to user code
 * Fix bug in 128-bit cmpxchg for BE Arm guests
 * Implement (no-op) HACR_EL2
 * Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

# gpg: Signature made Fri 15 Feb 2019 10:19:14 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190215: (25 commits)
  gdbstub: Send a reply to the vKill packet.
  target/arm: Add missing clear_tail calls
  target/arm: Use vector operations for saturation
  target/arm: Split out FPSCR.QC to a vector field
  target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
  target/arm: Split out flags setting from vfp compares
  target/arm: Fix arm_cpu_dump_state vs FPSCR
  target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
  target/arm: Remove neon min/max helpers
  target/arm: Use tcg integer min/max primitives for neon
  target/arm: Use vector minmax expanders for aarch32
  target/arm: Use vector minmax expanders for aarch64
  target/arm: Rely on optimization within tcg_gen_gvec_or
  hw/arm/armsse: Fix miswiring of expansion IRQs
  hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
  MAINTAINERS: Remove Peter Crosthwaite from various entries
  arm: Allow system registers for KVM guests to be changed by QEMU code
  linux-user/elfload: enable HWCAP_CPUID for AArch64
  target/arm: expose remaining CPUID registers as RAZ
  target/arm: expose MPIDR_EL1 to userspace
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/0266c739abbe...81dbcfa9e1d8