[Qemu-commits] [qemu/qemu] c7c7e1: target/mips: compare virtual addresse

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[Qemu-commits] [qemu/qemu] c7c7e1: target/mips: compare virtual addresse

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] c7c7e1: target/mips: compare virtual addresses in LL/SC se...
Date:	Thu, 14 Feb 2019 19:50:25 +0000 (UTC)
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c7c7e1e9a5e3f0a8a1dbff6e4ccfd21c2dc9f845
      
https://github.com/qemu/qemu/commit/c7c7e1e9a5e3f0a8a1dbff6e4ccfd21c2dc9f845
  Author: Leon Alrae <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/machine.c
    M target/mips/op_helper.c
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: compare virtual addresses in LL/SC sequence

Do only virtual addresses comaprisons in LL/SC sequence emulations.

Until this patch, physical addresses had been compared in SC part of
LL/SC sequence, even though such comparisons could be avoided. Getting
rid of them allows throwing away SC helpers and having common SC
implementations in user and system mode, avoiding the need for two
separate implementations selected by #ifdef CONFIG_USER_ONLY.

Correct guest software should not rely on LL/SC if they accesses the
same physical address via different virtual addresses or if page
mapping gets changed between LL/SC due to manipulating TLB entries.
MIPS Instruction Set Manual clearly says that an RMW sequence must
use the same address in the LL and SC (virtual address, physical
address, cacheability and coherency attributes must be identical).
Otherwise, the result of the SC is not predictable. This patch takes
advantage of this fact and removes the virtual->physical address
translation from SC helper.

lladdr served as Coprocessor 0 LLAddr register which captures physical
address of the most recent LL instruction, and also lladdr was used
for comparison with following SC physical address. This patch changes
the meaning of lladdr - now it will only keep the virtual address of
the most recent LL. Additionally, CP0_LLAddr field is introduced which
is the actual Coperocessor 0 LLAddr register that guest can access.

Signed-off-by: Leon Alrae <address@hidden>
Signed-off-by: Miodrag Dinic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Acked-by: Alex Bennée <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>


  Commit: 33a07fa2db66376e6ee780d4a8b064dc5118cf34
      
https://github.com/qemu/qemu/commit/33a07fa2db66376e6ee780d4a8b064dc5118cf34
  Author: Leon Alrae <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M linux-user/mips/cpu_loop.c
    M target/mips/cpu.h
    M target/mips/helper.c
    M target/mips/helper.h
    M target/mips/op_helper.c
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: reimplement SC instruction emulation and use cmpxchg

Completely rewrite conditional stores handling. Use cmpxchg.

This eliminates need for separate implementations of SC instruction
emulation for user and system emulation.

Signed-off-by: Leon Alrae <address@hidden>
Signed-off-by: Miodrag Dinic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Acked-by: Alex Bennée <address@hidden>
Tested-by: Emilio G. Cota <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 215581bdf1659c80645125df56cd2daa40de3d97
      
https://github.com/qemu/qemu/commit/215581bdf1659c80645125df56cd2daa40de3d97
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M hw/mips/mips_int.c
    M target/mips/op_helper.c

  Log Message:
  -----------
  hw/mips_int: hold BQL for all interrupt requests

Make sure BQL is held for all interrupt requests.

For MTTCG-enabled configurations, handling soft and hard interrupts
between vCPUs must be properly locked. By acquiring BQL, make sure
all paths triggering an IRQ are synchronized.

Signed-off-by: Miodrag Dinic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Acked-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 41931c0137eeeff1303f254ed610217c0fa00313
      
https://github.com/qemu/qemu/commit/41931c0137eeeff1303f254ed610217c0fa00313
  Author: Goran Ferenc <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: hold BQL in mips_vpe_wake()

Hold BQL whenever mips_vpe_wake() is invoked.

Without this patch, MIPS MT with MTTCG enabled triggers an abort in
tcg_handle_interrupt() due to an unlocked access to cpu_interrupt().
This patch makes sure that the BQL is held in this case.

Signed-off-by: Goran Ferenc <address@hidden>
Signed-off-by: Miodrag Dinic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Acked-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: f5117fd28552fe3fe32ef0495582b1caaef7a28d
      
https://github.com/qemu/qemu/commit/f5117fd28552fe3fe32ef0495582b1caaef7a28d
  Author: Miodrag Dinic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M hw/misc/mips_cpc.c

  Log Message:
  -----------
  hw/mips_cpc: kick a VP when putting it into Run statewq

While testing mttcg VP0 could get stuck in a loop waiting for other
VPs to come up (which never actually happens). To fix this, kick VPs
while they are being powered up by Cluster Power Controller in an
async task which is triggered once the host thread is being spawned.

Signed-off-by: Miodrag Dinic <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Acked-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 0454728c2283097cfa3e4e26d459725fa2c67f10
      
https://github.com/qemu/qemu/commit/0454728c2283097cfa3e4e26d459725fa2c67f10
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M configure
    M target/mips/cpu.h

  Log Message:
  -----------
  target/mips: introduce MTTCG-enabled builds

Introduce MTTCG-enabled QEMU builds for mips32, mipsn32, and mips64.

Signed-off-by: Miodrag Dinic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Acked-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 51a0e80c6ef4a3da3c2bf27f09af7eec821fcb3b
      
https://github.com/qemu/qemu/commit/51a0e80c6ef4a3da3c2bf27f09af7eec821fcb3b
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    R tests/tcg/mips/mips64-dspr2/.directory

  Log Message:
  -----------
  tests/tcg: target/mips: Remove an unnecessary file

Remove a file that was added long time ago by mistake. The commit
that introduced this file was commit d70080c4 (from 2012).

Reviewed-by: Aleksandar Rikalo <address@hidden>
Acked-by: Alex Bennée <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: d33f67286159f4f34fe034e8696fb7d2fb8245df
      
https://github.com/qemu/qemu/commit/d33f67286159f4f34fe034e8696fb7d2fb8245df
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    A tests/tcg/mips/include/test_inputs.h

  Log Message:
  -----------
  tests/tcg: target/mips: Add a header with test inputs

The file tests/tcg/mips/include/test_inputs.h is planned to
contain various test inputs. For now, it contains 64 128-bit
pattern inputs (alternating groups od ones and zeroes) and
16 128-bit random inputs.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 08857c882d1da40793c3be27ae78cb3752902856
      
https://github.com/qemu/qemu/commit/08857c882d1da40793c3be27ae78cb3752902856
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    A tests/tcg/mips/include/test_utils.h

  Log Message:
  -----------
  tests/tcg: target/mips: Add a header with test utilities

Add a header that contains test utilities. For now, it contains
only a function for checking and printing test results for bit
counting and similar MSA instructions.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 85c2a393005656e9712959ca95c9be1e9aee4629
      
https://github.com/qemu/qemu/commit/85c2a393005656e9712959ca95c9be1e9aee4629
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    A tests/tcg/mips/include/wrappers_msa.h

  Log Message:
  -----------
  tests/tcg: target/mips: Add wrappers for MSA bit counting instructions

Add a header that contains wrappers around MSA instructions assembler
invocations. For now, only bit counting instructions (NLOC, NLZC, and
PCNT; each in four data format flavors) are supported.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: b62592ab655a6f6508908010d37f962bf5b2053f
      
https://github.com/qemu/qemu/commit/b62592ab655a6f6508908010d37f962bf5b2053f
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nloc_b.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nloc_d.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nloc_h.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nloc_w.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nlzc_b.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nlzc_d.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nlzc_h.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nlzc_w.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_pcnt_b.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_pcnt_d.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_pcnt_h.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_pcnt_w.c

  Log Message:
  -----------
  tests/tcg: target/mips: Add tests for MSA bit counting instructions

Add tests for MSA bit counting instructions. This includes following
instructions:

  * NLOC.B - number of leading ones (bytes)
  * NLOC.H - number of leading ones (halfwords)
  * NLOC.W - number of leading ones (words)
  * NLOC.D - number of leading ones (doublewords)
  * NLZC.B - number of leading zeros (bytes)
  * NLZC.H - number of leading zeros (halfwords)
  * NLZC.W - number of leading zeros (words)
  * NLZC.D - number of leading zeros (doublewords)
  * PCNT.B - population count / number of ones (bytes)
  * PCNT.H - population count / number of ones (halfwords)
  * PCNT.W - population count / number of ones (words)
  * PCNT.D - population count / number of ones (doublewords)

Each test consists of 80 test cases, so altogether there are 960 test
cases.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: afdc3c515ad215ddf02c0f1afe9e06def8212588
      
https://github.com/qemu/qemu/commit/afdc3c515ad215ddf02c0f1afe9e06def8212588
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M tests/tcg/mips/include/wrappers_msa.h

  Log Message:
  -----------
  tests/tcg: target/mips: Add wrappers for MSA interleave instructions

Add wrappers for MSA interleave instructions.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: fc76f486677e9aa4403a673cf76ede0c20273ef6
      
https://github.com/qemu/qemu/commit/fc76f486677e9aa4403a673cf76ede0c20273ef6
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_b.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_d.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_h.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_w.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_b.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_d.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_h.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_w.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvod_b.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvod_d.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvod_h.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvod_w.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvr_b.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvr_d.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvr_h.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvr_w.c

  Log Message:
  -----------
  tests/tcg: target/mips: Add tests for MSA interleave instructions

Add tests for MSA interleave instructions. This includes following
instructions:

  * ILVEV.B - interleave even (bytes)
  * ILVEV.H - interleave even (halfwords)
  * ILVEV.W - interleave even (words)
  * ILVEV.D - interleave even (doublewords)
  * ILVOD.B - interleave odd (bytes)
  * ILVOD.H - interleave odd (halfwords)
  * ILVOD.W - interleave odd (words)
  * ILVOD.D - interleave odd (doublewords)
  * ILVL.B - interleave left (bytes)
  * ILVL.H - interleave left (halfwords)
  * ILVL.W - interleave left (words)
  * ILVL.D - interleave left (doublewords)
  * ILVR.B - interleave right (bytes)
  * ILVR.H - interleave right (halfwords)
  * ILVR.W - interleave right (words)
  * ILVR.D - interleave right (doublewords)

Each test consists of 80 test cases, so altogether there are 1280
test cases.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: db37850bb4ead8080da878c1c0eb04d33c81bfd4
      
https://github.com/qemu/qemu/commit/db37850bb4ead8080da878c1c0eb04d33c81bfd4
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M tests/tcg/mips/include/wrappers_msa.h

  Log Message:
  -----------
  tests/tcg: target/mips: Add wrappers for MSA logic instructions

Add wrappers for MSA logic instructions.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: ba632924450faf6741d299f8feed8150a0c6f884
      
https://github.com/qemu/qemu/commit/ba632924450faf6741d299f8feed8150a0c6f884
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    A tests/tcg/mips/user/ase/msa/logic/test_msa_and_v.c
    A tests/tcg/mips/user/ase/msa/logic/test_msa_nor_v.c
    A tests/tcg/mips/user/ase/msa/logic/test_msa_or_v.c
    A tests/tcg/mips/user/ase/msa/logic/test_msa_xor_v.c

  Log Message:
  -----------
  tests/tcg: target/mips: Add tests for MSA logic instructions

Add tests for MSA logic instructions. This includes following
instructions:

  * AND.V - logical AND
  * NOR.V - logical NOR
  * OR.V - logical OR
  * XOR.V - logical XOR

Each test consists of 80 test cases, so altogether there are 320
test cases.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 0266c739abbed804deabb4ccde2aa449466ac3b4
      
https://github.com/qemu/qemu/commit/0266c739abbed804deabb4ccde2aa449466ac3b4
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M configure
    M hw/mips/mips_int.c
    M hw/misc/mips_cpc.c
    M linux-user/mips/cpu_loop.c
    M target/mips/cpu.h
    M target/mips/helper.c
    M target/mips/helper.h
    M target/mips/machine.c
    M target/mips/op_helper.c
    M target/mips/translate.c
    A tests/tcg/mips/include/test_inputs.h
    A tests/tcg/mips/include/test_utils.h
    A tests/tcg/mips/include/wrappers_msa.h
    R tests/tcg/mips/mips64-dspr2/.directory
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nloc_b.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nloc_d.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nloc_h.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nloc_w.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nlzc_b.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nlzc_d.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nlzc_h.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_nlzc_w.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_pcnt_b.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_pcnt_d.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_pcnt_h.c
    A tests/tcg/mips/user/ase/msa/bit-counting/test_msa_pcnt_w.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_b.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_d.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_h.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvev_w.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_b.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_d.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_h.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvl_w.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvod_b.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvod_d.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvod_h.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvod_w.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvr_b.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvr_d.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvr_h.c
    A tests/tcg/mips/user/ase/msa/interleave/test_msa_ilvr_w.c
    A tests/tcg/mips/user/ase/msa/logic/test_msa_and_v.c
    A tests/tcg/mips/user/ase/msa/logic/test_msa_nor_v.c
    A tests/tcg/mips/user/ase/msa/logic/test_msa_or_v.c
    A tests/tcg/mips/user/ase/msa/logic/test_msa_xor_v.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' 
into staging

MIPS queue for February 14th, 2019

# gpg: Signature made Thu 14 Feb 2019 16:48:39 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-feb-14-2019:
  tests/tcg: target/mips: Add tests for MSA logic instructions
  tests/tcg: target/mips: Add wrappers for MSA logic instructions
  tests/tcg: target/mips: Add tests for MSA interleave instructions
  tests/tcg: target/mips: Add wrappers for MSA interleave instructions
  tests/tcg: target/mips: Add tests for MSA bit counting instructions
  tests/tcg: target/mips: Add wrappers for MSA bit counting instructions
  tests/tcg: target/mips: Add a header with test utilities
  tests/tcg: target/mips: Add a header with test inputs
  tests/tcg: target/mips: Remove an unnecessary file
  target/mips: introduce MTTCG-enabled builds
  hw/mips_cpc: kick a VP when putting it into Run statewq
  target/mips: hold BQL in mips_vpe_wake()
  hw/mips_int: hold BQL for all interrupt requests
  target/mips: reimplement SC instruction emulation and use cmpxchg
  target/mips: compare virtual addresses in LL/SC sequence

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/0d3e41d5efd6...0266c739abbe
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