[Qemu-commits] [qemu/qemu] 63b695: hw/riscv/virt: Increase the number of interrupts

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 63b695f2aa505d11542ecd8a272d42019a37a676
      
https://github.com/qemu/qemu/commit/63b695f2aa505d11542ecd8a272d42019a37a676
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv/virt: Increase the number of interrupts

Increase the number of interrupts to match the HiFive Unleashed board.

Signed-off-by: Alistair Francis <address@hidden>
Tested-by: Guenter Roeck <address@hidden>
Tested-by: Andrea Bolognani <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: bb1973aadb78bfb653287421d9df8ade1accc4af
      
https://github.com/qemu/qemu/commit/bb1973aadb78bfb653287421d9df8ade1accc4af
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv/virt: Adjust memory layout spacing

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Logan Gunthorpe <address@hidden>
Tested-by: Guenter Roeck <address@hidden>
Tested-by: Andrea Bolognani <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6d56e39649808696b2321cbd200dd7ccaa7ef7fe
      
https://github.com/qemu/qemu/commit/6d56e39649808696b2321cbd200dd7ccaa7ef7fe
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M default-configs/riscv32-softmmu.mak
    M default-configs/riscv64-softmmu.mak
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv/virt: Connect the gpex PCIe

Connect the gpex PCIe device based on the device tree included in the
HiFive Unleashed ROM.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Logan Gunthorpe <address@hidden>
Reviewed-by: Logan Gunthorpe <address@hidden>
Tested-by: Guenter Roeck <address@hidden>
Tested-by: Andrea Bolognani <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a9a0c2d1235a25049ceddb666dec66ba3f59a791
      
https://github.com/qemu/qemu/commit/a9a0c2d1235a25049ceddb666dec66ba3f59a791
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M default-configs/riscv32-softmmu.mak
    M default-configs/riscv64-softmmu.mak

  Log Message:
  -----------
  riscv: Enable VGA and PCIE_VGA

Enable compile support for VGA devices. This allows the user to conenct
a display by adding '-device bochs-display -display sdl' to their
command line argument.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Logan Gunthorpe <address@hidden>
Tested-by: Andrea Bolognani <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: fe93582cf52ee67f6ab5a59051d354344010cfdc
      
https://github.com/qemu/qemu/commit/fe93582cf52ee67f6ab5a59051d354344010cfdc
  Author: Anup Patel <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  sifive_u: Add clock DT node for GEM ethernet

The GEM ethernet on SiFive unleashed has fixed input clock
of 125MHz as-per SiFive FU540 manual. This patch updates FDT
generation for QEMU sifive_u machine to provide fixed-rate
clock for GEM ethernet.

Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6c60757eb667c5c5b4a1f6ce3eff874b83bcd734
      
https://github.com/qemu/qemu/commit/6c60757eb667c5c5b4a1f6ce3eff874b83bcd734
  Author: Anup Patel <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  sifive_u: Set 'clock-frequency' DT property for SiFive UART

The 'clock-frequency' DT property is required by U-Boot to compute
the divider value. This patch sets the 'clock-frequency' DT property
of the SiFive UART device tree node (similar to virt machine).

Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 9543fdaf223aac0313638752abfb3d6c2cf2169c
      
https://github.com/qemu/qemu/commit/9543fdaf223aac0313638752abfb3d6c2cf2169c
  Author: Michael Clark <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Add hartid and \n to interrupt logging

Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ef9e41df680a494dec92fe8d166cb2bc531b29a4
      
https://github.com/qemu/qemu/commit/ef9e41df680a494dec92fe8d166cb2bc531b29a4
  Author: Michael Clark <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M hw/riscv/sifive_clint.c

  Log Message:
  -----------
  RISC-V: Fix CLINT timecmp low 32-bit writes

A missing shift made updates to the low order bits
of timecmp erroneously copy the old low order bits
into the high order bits of the 64-bit timecmp
register. Add the missing shift and rename timecmp
local variables to timecmp_hi and timecmp_lo.

This bug didn't show up as the low order bits are
usually written first followed by the high order
bits meaning the high order bits contained an invalid
value between the timecmp_lo and timecmp_hi update.

Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Co-Authored-by: Johannes Haring <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e41848e5c9245947c09fb0cf3e160ec9350907f4
      
https://github.com/qemu/qemu/commit/e41848e5c9245947c09fb0cf3e160ec9350907f4
  Author: Michael Clark <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M hw/riscv/sifive_plic.c

  Log Message:
  -----------
  RISC-V: Fix PLIC pending bitfield reads

The address calculation for the pending bitfield had
a copy paste bug. This bug went unnoticed because the Linux
PLIC driver does not read the pending bitfield, rather it
reads pending interrupt numbers from the claim register
and writes acknowledgements back to the claim register.

Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Reported-by: Vincent Siles <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 194eef09d06358ea50b52340df853e9beeccce15
      
https://github.com/qemu/qemu/commit/194eef09d06358ea50b52340df853e9beeccce15
  Author: Michael Clark <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  RISC-V: Enable second UART on sifive_e and sifive_u

Previously the second UARTs on the sifive_e and sifive_u machines
where disabled due to check-qtest-riscv32 and check-qtest-riscv64
failures. Recent changes in the QEMU core serial code have
resolved these failures so the second UARTs can be instantiated.

Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 40061ac0bc5bdfcfa1234dbf8e2a880fd9fc4c2e
      
https://github.com/qemu/qemu/commit/40061ac0bc5bdfcfa1234dbf8e2a880fd9fc4c2e
  Author: Nathaniel Graff <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M hw/riscv/sifive_uart.c
    M include/hw/riscv/sifive_uart.h

  Log Message:
  -----------
  sifive_uart: Implement interrupt pending register

The watermark bits are set in the interrupt pending register according
to the configuration of txcnt and rxcnt in the txctrl and rxctrl
registers.

Since the UART TX does not implement a FIFO, the txwm bit is set as long
as the TX watermark level is greater than zero.

Signed-off-by: Nathaniel Graff <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 71a150bc914ef154d1321cc3602a4e80a433fc52
      
https://github.com/qemu/qemu/commit/71a150bc914ef154d1321cc3602a4e80a433fc52
  Author: Anup Patel <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv/pmp.c: Fix pmp_decode_napot()

Currently, start and end address of a PMP region are not decoded
correctly by pmp_decode_napot().

Let's say we have a 128KB PMP region with base address as 0x80000000.
Now, the PMPADDRx CSR value for this region will be 0x20003fff.

The current pmp_decode_napot() implementation will decode PMPADDRx
CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should
have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff.

This patch fixes the base value decoding in pmp_decode_napot() when
PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff).

Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 41fbbba7753457331d971887a74d9a96066f65ba
      
https://github.com/qemu/qemu/commit/41fbbba7753457331d971887a74d9a96066f65ba
  Author: Mao Zhongyi <address@hidden>
  Date:   2018-12-20 (Thu, 20 Dec 2018)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  riscv/cpu: use device_class_set_parent_realize

Signed-off-by: Mao Zhongyi <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7b91ae7d7944056c5e8045342e4039e978e43c82
      
https://github.com/qemu/qemu/commit/7b91ae7d7944056c5e8045342e4039e978e43c82
  Author: Palmer Dabbelt <address@hidden>
  Date:   2018-12-21 (Fri, 21 Dec 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Mark RISC-V as Supported

There's at least two of us that are paid to work on this.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 20d6c7312f1b812bb9c750f4087f69ac8485cc90
      
https://github.com/qemu/qemu/commit/20d6c7312f1b812bb9c750f4087f69ac8485cc90
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-03 (Thu, 03 Jan 2019)

  Changed paths:
    M MAINTAINERS
    M default-configs/riscv32-softmmu.mak
    M default-configs/riscv64-softmmu.mak
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_plic.c
    M hw/riscv/sifive_u.c
    M hw/riscv/sifive_uart.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/sifive_uart.h
    M include/hw/riscv/virt.h
    M target/riscv/cpu.c
    M target/riscv/cpu_helper.c
    M target/riscv/pmp.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1' 
into staging

RISC-V Changes for 3.2, Part 1

This pull request contains the first set of RISC-V patches I'd like to
target for the 3.2 development cycle.  It's really just a collection of
bug fixes with one major new feature: PCIe can now be attached to RISC-V
guests.

This has passed my usual test of booting the latest Linux RC into a
Fedora disk image on the virt machine.

# gpg: Signature made Fri 21 Dec 2018 16:01:29 GMT
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <address@hidden>"
# gpg:                 aka "Palmer Dabbelt <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-3.2-part1:
  MAINTAINERS: Mark RISC-V as Supported
  riscv/cpu: use device_class_set_parent_realize
  target/riscv/pmp.c: Fix pmp_decode_napot()
  sifive_uart: Implement interrupt pending register
  RISC-V: Enable second UART on sifive_e and sifive_u
  RISC-V: Fix PLIC pending bitfield reads
  RISC-V: Fix CLINT timecmp low 32-bit writes
  RISC-V: Add hartid and \n to interrupt logging
  sifive_u: Set 'clock-frequency' DT property for SiFive UART
  sifive_u: Add clock DT node for GEM ethernet
  riscv: Enable VGA and PCIE_VGA
  hw/riscv/virt: Connect the gpex PCIe
  hw/riscv/virt: Adjust memory layout spacing
  hw/riscv/virt: Increase the number of interrupts

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/1b3e80082bcd...20d6c7312f1b
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