[Qemu-commits] [qemu/qemu] 6d06fd: elf.h: Add the RISCV ELF magic numbers

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6d06fdd10eecc89d73af0b9e3a7cf1be64a9988b
      
https://github.com/qemu/qemu/commit/6d06fdd10eecc89d73af0b9e3a7cf1be64a9988b
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M include/elf.h

  Log Message:
  -----------
  elf.h: Add the RISCV ELF magic numbers

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: f936eac8082ece746c543386a234087d0b32e419
      
https://github.com/qemu/qemu/commit/f936eac8082ece746c543386a234087d0b32e419
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M MAINTAINERS
    A linux-user/host/riscv32/hostdep.h

  Log Message:
  -----------
  linux-user: Add host dependency for RISC-V 32-bit

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 511f3138e4af5c1022e0f746cb4f5454fd58fab0
      
https://github.com/qemu/qemu/commit/511f3138e4af5c1022e0f746cb4f5454fd58fab0
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M MAINTAINERS
    A linux-user/host/riscv64/hostdep.h

  Log Message:
  -----------
  linux-user: Add host dependency for RISC-V 64-bit

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e4041f669fc7abb966247d194743e2d91fdc7d5b
      
https://github.com/qemu/qemu/commit/e4041f669fc7abb966247d194743e2d91fdc7d5b
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M include/exec/poison.h

  Log Message:
  -----------
  exec: Add RISC-V GCC poison macro

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: fb1f70f3685bae613d91626578bce96590ed2cb7
      
https://github.com/qemu/qemu/commit/fb1f70f3685bae613d91626578bce96590ed2cb7
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M MAINTAINERS
    A tcg/riscv/tcg-target.h

  Log Message:
  -----------
  tcg/riscv: Add the tcg-target.h file

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 505e75c592825e3a8fed38af252fa4425e2c2b09
      
https://github.com/qemu/qemu/commit/505e75c592825e3a8fed38af252fa4425e2c2b09
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    A tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the tcg target registers

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 8ce23a131254387bbd6135802aef3c6dce010249
      
https://github.com/qemu/qemu/commit/8ce23a131254387bbd6135802aef3c6dce010249
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add support for the constraints

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 54a9ce0f683ab69b0a16e59f5ef28c1ded604def
      
https://github.com/qemu/qemu/commit/54a9ce0f683ab69b0a16e59f5ef28c1ded604def
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the immediate encoders

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: bedf14e335f5cb1339e9f35834ca7fe49d62a083
      
https://github.com/qemu/qemu/commit/bedf14e335f5cb1339e9f35834ca7fe49d62a083
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the instruction emitters

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: dfa8e74f946347accb834da0f47126c39394c31f
      
https://github.com/qemu/qemu/commit/dfa8e74f946347accb834da0f47126c39394c31f
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the relocation functions

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 6cd2eda39f648ed398b0dca69cd7aaf6be50e30d
      
https://github.com/qemu/qemu/commit/6cd2eda39f648ed398b0dca69cd7aaf6be50e30d
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the mov and movi instruction

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 27fd64144bebc34a815fd8a69af790b080e80c61
      
https://github.com/qemu/qemu/commit/27fd64144bebc34a815fd8a69af790b080e80c61
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the extract instructions

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 61535d49881a93b9c765eef0290a47f310eb9067
      
https://github.com/qemu/qemu/commit/61535d49881a93b9c765eef0290a47f310eb9067
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the out load and store instructions

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 28ca738e9db89abffe329e8924a141b90c1b91e1
      
https://github.com/qemu/qemu/commit/28ca738e9db89abffe329e8924a141b90c1b91e1
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the add2 and sub2 instructions

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 15840069e17e133e0295c183565d0101334b8476
      
https://github.com/qemu/qemu/commit/15840069e17e133e0295c183565d0101334b8476
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add branch and jump instructions

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: efbea94c76b25d9655900e744799ad542527a45f
      
https://github.com/qemu/qemu/commit/efbea94c76b25d9655900e744799ad542527a45f
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add slowpath load and store instructions

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 03a7d0213d6b6ffd0781dbd0c41ba73160bec9a1
      
https://github.com/qemu/qemu/commit/03a7d0213d6b6ffd0781dbd0c41ba73160bec9a1
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add direct load and store instructions

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: bdf503819ee188765f0249cb4507c3b2646ae884
      
https://github.com/qemu/qemu/commit/bdf503819ee188765f0249cb4507c3b2646ae884
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the out op decoder

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 92c041c59b99fbc35bdf4d5520fcaff80dc69ee0
      
https://github.com/qemu/qemu/commit/92c041c59b99fbc35bdf4d5520fcaff80dc69ee0
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the prologue generation and register the JIT

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 7a5549f2aea84bf8c71c6eaa438b4bb84e9ad967
      
https://github.com/qemu/qemu/commit/7a5549f2aea84bf8c71c6eaa438b4bb84e9ad967
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Add the target init code

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 464e447a0c4fbda2c5adce9a1b0f96800648a36f
      
https://github.com/qemu/qemu/commit/464e447a0c4fbda2c5adce9a1b0f96800648a36f
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  tcg: Add RISC-V cpu signal handler

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 91468b2703ee0e4dcd7439dec8ca60d6cf8270ac
      
https://github.com/qemu/qemu/commit/91468b2703ee0e4dcd7439dec8ca60d6cf8270ac
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M disas.c

  Log Message:
  -----------
  disas: Add RISC-V support

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: c4f8054381348385529dc4a5928bbf2226144040
      
https://github.com/qemu/qemu/commit/c4f8054381348385529dc4a5928bbf2226144040
  Author: Alistair Francis <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M configure

  Log Message:
  -----------
  configure: Add support for building RISC-V host

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 11cee55f18a02637945f12718237506abb8073b2
      
https://github.com/qemu/qemu/commit/11cee55f18a02637945f12718237506abb8073b2
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M disas/microblaze.c

  Log Message:
  -----------
  disas/microblaze: Remove unused REG_SP macro

This causes a build error with debian sid, riscv64 host:

disas/microblaze.c:179: error: "REG_SP" redefined [-Werror]
 #define REG_SP  1 /* stack pointer */

In file included from /usr/include/signal.h:306,
           from include/qemu/osdep.h:101,
           from disas/microblaze.c:36:
/usr/include/riscv64-linux-gnu/sys/ucontext.h:36: note: this is the location of 
the previous definition
 # define REG_SP 2

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b8c92c6d2969e88b252f1d2351237a87981d1e74
      
https://github.com/qemu/qemu/commit/b8c92c6d2969e88b252f1d2351237a87981d1e74
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M linux-user/host/riscv64/hostdep.h
    A linux-user/host/riscv64/safe-syscall.inc.S

  Log Message:
  -----------
  linux-user: Add safe_syscall for riscv64 host

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 3b50352b05eeafeb95cccd770f7aaba00bbdf6fe
      
https://github.com/qemu/qemu/commit/3b50352b05eeafeb95cccd770f7aaba00bbdf6fe
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Renumber TCG_CALL_* flags

Previously, the low 4 bits were used for TCG_CALL_TYPE_MASK,
which was removed in 6a18ae2d2947532d5c26439548afa0481c4529f9.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 15d7409260498505e991e7b9d87118627165e613
      
https://github.com/qemu/qemu/commit/15d7409260498505e991e7b9d87118627165e613
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M include/exec/helper-head.h
    M include/exec/helper-tcg.h
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add TCG_CALL_NO_RETURN

Remember which helpers have been marked noreturn.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d88a117eaa39b1d0eb1a79fe84c81840a39eb233
      
https://github.com/qemu/qemu/commit/d88a117eaa39b1d0eb1a79fe84c81840a39eb233
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg-op.c
    M tcg/tcg-op.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Reference count labels

Increment when adding branches, and decrement when removing them.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b4fc67c7afd2c338d6e7c73a7f428dfe05ae0603
      
https://github.com/qemu/qemu/commit/b4fc67c7afd2c338d6e7c73a7f428dfe05ae0603
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add reachable_code_pass

Delete trivially dead code that follows unconditional branches and
noreturn helpers.  These can occur either via optimization or via
the structure of a target's translator following an exception.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b016486e7baddb43cfc1e51909b05cde9cf82e0c
      
https://github.com/qemu/qemu/commit/b016486e7baddb43cfc1e51909b05cde9cf82e0c
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add preferred_reg argument to tcg_reg_alloc

This new argument will aid register allocation by indicating how
the temporary will be used in future.  If the preference cannot
be satisfied, fall back to the constraints of the current insn.

Short circuit the preference when it cannot be satisfied or if
it does not further constrain the operation.

With an eye toward optimizing function call sequences, optimize
for the preferred_reg set containing a single register.

For the moment, all users pass 0 for preference.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b722452aefb089e003b16946a4d73bad1fd3b79b
      
https://github.com/qemu/qemu/commit/b722452aefb089e003b16946a4d73bad1fd3b79b
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add preferred_reg argument to temp_load

Pass this through to tcg_reg_alloc.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 98b4e186c1ccb8f1868c61a33a3be8c2b82654f3
      
https://github.com/qemu/qemu/commit/98b4e186c1ccb8f1868c61a33a3be8c2b82654f3
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add preferred_reg argument to temp_sync

Pass this through to tcg_reg_alloc.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: ba87719cd267e6f07b17f6cda08246bf483146d4
      
https://github.com/qemu/qemu/commit/ba87719cd267e6f07b17f6cda08246bf483146d4
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi

Pass this through to temp_sync.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 69e3706d2b473815e382552e729d12590339e0ac
      
https://github.com/qemu/qemu/commit/69e3706d2b473815e382552e729d12590339e0ac
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add output_pref to TCGOp

Allocate storage for, but do not yet fill in, per-opcode
preferences for the output operands.  Pass it in to the
register allocation routines for output operands.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d62816f2db439b2dd761c674f0256f21d9dd2ed0
      
https://github.com/qemu/qemu/commit/d62816f2db439b2dd761c674f0256f21d9dd2ed0
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Improve register allocation for matching constraints

Try harder to honor the output_pref.  When we're forced to allocate
a second register for the input, it does not need to use the input
constraint; that will be honored by the register we allocate for the
output and a move is already required.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 1894f69a612b35c2a39b44a824da04d74bfe324a
      
https://github.com/qemu/qemu/commit/1894f69a612b35c2a39b44a824da04d74bfe324a
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Dump register preference info with liveness

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 152c35aab43213335e1ae8b865d259c0222dd110
      
https://github.com/qemu/qemu/commit/152c35aab43213335e1ae8b865d259c0222dd110
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Reindent parts of liveness_pass_1

There are two blocks of the form

    if (foo) {
  stuff1;
  goto bar;
    } else {
    baz:
  stuff2;
    }

which have unnecessary and confusing indentation.
Remove the else and unindent stuff2.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 2616c8082143373e794b62444bf81754f50dbf6b
      
https://github.com/qemu/qemu/commit/2616c8082143373e794b62444bf81754f50dbf6b
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Rename and adjust liveness_pass_1 helpers

No need for a "tcg_" prefix for a static function; we already
have another "la_" prefix for indicating liveness analysis.
Pass in nb_globals and nb_temps, as we will already have them
in registers for other loops within the parent function.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: f65a061c39cc4f9d088201031050e42eb23d5b2a
      
https://github.com/qemu/qemu/commit/f65a061c39cc4f9d088201031050e42eb23d5b2a
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Split out more subroutines from liveness_pass_1

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: ae36a246ed1a0e96c6c4f478f03d047dfa3a8898
      
https://github.com/qemu/qemu/commit/ae36a246ed1a0e96c6c4f478f03d047dfa3a8898
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg-opc.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add TCG_OPF_BB_EXIT

Use this to notice the opcodes that exit the TB, which implies
that local temps are really dead and need not be synced.

Previously we so marked the true end of the TB, but that was
immediately overwritten by the la_bb_end invoked by any
TCG_OPF_BB_END opcode, like exit_tb.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 25f49c5f1508ddf081ce89fa6bbfd87a51eea37b
      
https://github.com/qemu/qemu/commit/25f49c5f1508ddf081ce89fa6bbfd87a51eea37b
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Record register preferences during liveness

With these preferences, we can arrange for function call arguments to
be computed into the proper registers instead of requiring extra moves.

Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 4250da10923347c9ee907f8d72bd93dfa5ee8742
      
https://github.com/qemu/qemu/commit/4250da10923347c9ee907f8d72bd93dfa5ee8742
  Author: Richard Henderson <address@hidden>
  Date:   2018-12-26 (Wed, 26 Dec 2018)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Improve call argument loading

Free the argument register only after we have verified that the
temporary is not already in that register.  This case is likely
now that we are back propagating the preferred register.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 1b3e80082bcd9b760113bbc023496cd22efad2dc
      
https://github.com/qemu/qemu/commit/1b3e80082bcd9b760113bbc023496cd22efad2dc
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-03 (Thu, 03 Jan 2019)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/user-exec.c
    M configure
    M disas.c
    M disas/microblaze.c
    M include/elf.h
    M include/exec/helper-head.h
    M include/exec/helper-tcg.h
    M include/exec/poison.h
    A linux-user/host/riscv32/hostdep.h
    A linux-user/host/riscv64/hostdep.h
    A linux-user/host/riscv64/safe-syscall.inc.S
    A tcg/riscv/tcg-target.h
    A tcg/riscv/tcg-target.inc.c
    M tcg/tcg-op.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181226' into staging

Host support for riscv64.
Dead code elimination pass.
Register allocation improvements.

# gpg: Signature made Tue 25 Dec 2018 20:52:34 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <address@hidden>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20181226: (42 commits)
  tcg: Improve call argument loading
  tcg: Record register preferences during liveness
  tcg: Add TCG_OPF_BB_EXIT
  tcg: Split out more subroutines from liveness_pass_1
  tcg: Rename and adjust liveness_pass_1 helpers
  tcg: Reindent parts of liveness_pass_1
  tcg: Dump register preference info with liveness
  tcg: Improve register allocation for matching constraints
  tcg: Add output_pref to TCGOp
  tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi
  tcg: Add preferred_reg argument to temp_sync
  tcg: Add preferred_reg argument to temp_load
  tcg: Add preferred_reg argument to tcg_reg_alloc
  tcg: Add reachable_code_pass
  tcg: Reference count labels
  tcg: Add TCG_CALL_NO_RETURN
  tcg: Renumber TCG_CALL_* flags
  linux-user: Add safe_syscall for riscv64 host
  disas/microblaze: Remove unused REG_SP macro
  configure: Add support for building RISC-V host
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/9b2e891ec5cc...1b3e80082bcd
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