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[Qemu-commits] [qemu/qemu] 6f6928: target/mips: Define R5900 ISA, MMI AS
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[Qemu-commits] [qemu/qemu] 6f6928: target/mips: Define R5900 ISA, MMI ASE, and R5900 ... |
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Wed, 24 Oct 2018 10:56:24 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 6f692818a7b53630702d25a709cd61282fd139ad
https://github.com/qemu/qemu/commit/6f692818a7b53630702d25a709cd61282fd139ad
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants
The R5900 implements the 64-bit MIPS III instruction set except
DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV
instructions MOVN, MOVZ and PREF are implemented. It has the
R5900-specific three-operand instructions MADD, MADDU, MULT and
MULTU as well as pipeline 1 versions MULT1, MULTU1, DIV1, DIVU1,
MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1. A set of 93 128-bit
multimedia instructions specific to the R5900 is also implemented.
The Toshiba TX System RISC TX79 Core Architecture manual:
https://wiki.qemu.org/File:C790.pdf
describes the C790 processor that is a follow-up to the R5900. There
are a few notable differences in that the R5900 FPU
- is not IEEE 754-1985 compliant,
- does not implement double format, and
- its machine code is nonstandard.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 497f072b159effc4b19d9629e4818e6185be5776
https://github.com/qemu/qemu/commit/497f072b159effc4b19d9629e4818e6185be5776
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add R5900 Multimedia Instruction overview note
Add a comment on R5900 MMI ASE (short overview).
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: f99c0d6da3424dd48ad1f0345464f63515949be6
https://github.com/qemu/qemu/commit/f99c0d6da3424dd48ad1f0345464f63515949be6
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Define R5900 MMI class, and LQ and SQ opcode constants
Define MMI class, LQ, and SQ R5900 opdoces.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: d3297211720871cc5a61522ef1bd1523a451f3d3
https://github.com/qemu/qemu/commit/d3297211720871cc5a61522ef1bd1523a451f3d3
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants
Define MMI0, MMI1, MMI2, MMI3 subclass opcodes, and other opcodes of
instructions in MMI class.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 3ef65697a1a6ed8c8a6fa7b75f6f06362e2bc7d0
https://github.com/qemu/qemu/commit/3ef65697a1a6ed8c8a6fa7b75f6f06362e2bc7d0
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Define R5900 MMI0 opcode constants
Add definition of MI0 opcodes.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 7759654112f32c86cec8cafdbff8db5fc7f2e7f2
https://github.com/qemu/qemu/commit/7759654112f32c86cec8cafdbff8db5fc7f2e7f2
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Define R5900 MMI1 opcode constants
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 6c03ef6aaa7b4c404d61d71fe3420a93ab6b54f7
https://github.com/qemu/qemu/commit/6c03ef6aaa7b4c404d61d71fe3420a93ab6b54f7
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Define R5900 MMI2 opcode constants
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: dd581bf97d58d999fc58634c12251c1ea632a75d
https://github.com/qemu/qemu/commit/dd581bf97d58d999fc58634c12251c1ea632a75d
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Define R5900 MMI3 opcode constants
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: bb41e74b66a8879ba5c23db145039faa27df5766
https://github.com/qemu/qemu/commit/bb41e74b66a8879ba5c23db145039faa27df5766
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR
Add placeholder for SQ instruction, handle RDHWR.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: f08099ad7a4dd32e12a3f9d4b4b04c32d7522b03
https://github.com/qemu/qemu/commit/f08099ad7a4dd32e12a3f9d4b4b04c32d7522b03
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add a placeholder for R5900 LQ
Add a placeholder for LQ instruction.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 71b8a6b3f3d89283b094e04962c077aa01401438
https://github.com/qemu/qemu/commit/71b8a6b3f3d89283b094e04962c077aa01401438
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add a placeholder for R5900 MMI instruction class
Add a placeholder for MMI class. This is the main palceholder for
MMI ASE.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 88eafe0b28c8e88ed6d38eb27dbf482f9c885745
https://github.com/qemu/qemu/commit/88eafe0b28c8e88ed6d38eb27dbf482f9c885745
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add a placeholder for R5900 MMI0 instruction subclass
Add a placeholder for MMI0 subclass.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 7a803ca23a6d6ac0d1d34469cd3f010a66cd381a
https://github.com/qemu/qemu/commit/7a803ca23a6d6ac0d1d34469cd3f010a66cd381a
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add a placeholder for R5900 MMI1 instruction subclass
Add a placeholder for MM1 subclass.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 6c1e48d38a2d26cca2d2b00f331a4ac7dbfae3ca
https://github.com/qemu/qemu/commit/6c1e48d38a2d26cca2d2b00f331a4ac7dbfae3ca
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add a placeholder for R5900 MMI2 instruction subclass
Add a placeholder for MMI2 subclass.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: ec1944fc8eb862d48a0c74671105ce13acbc9c9e
https://github.com/qemu/qemu/commit/ec1944fc8eb862d48a0c74671105ce13acbc9c9e
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add a placeholder for R5900 MMI3 instruction subclass
Add a placeholder for MMI3 subclass.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 21e8e8b230af38b6bd8c953fa5f31e4a5a128e1c
https://github.com/qemu/qemu/commit/21e8e8b230af38b6bd8c953fa5f31e4a5a128e1c
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Support R5900 three-operand MULT and MULTU instructions
The three-operand MULT and MULTU are the only R5900-specific
instructions emitted by GCC 7.3. The R5900 also implements the three-
operand MADD and MADDU instructions, but they are omitted in QEMU for
now since they are absent in programs compiled by current GCC versions.
Likewise, the R5900-specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1
are omitted here as well.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 06de726b2d4da185dfec9d06b5f1032059ad3554
https://github.com/qemu/qemu/commit/06de726b2d4da185dfec9d06b5f1032059ad3554
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
Add support for MULT1 and MULTU1 instructions.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 8d927f7cb4b3ec06d6a7cf71221fd6a48e9a8fb5
https://github.com/qemu/qemu/commit/8d927f7cb4b3ec06d6a7cf71221fd6a48e9a8fb5
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
Add support for MFLO1, MTLO1, MFHI1 and MTHI1 instructions.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: be9c42c90d162100a63111ddeb8bfe50be897873
https://github.com/qemu/qemu/commit/be9c42c90d162100a63111ddeb8bfe50be897873
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Support R5900 DIV1 and DIVU1 instructions
Add support for DIV1 and DIVU1 instructions.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 5601e6217d90ed322b4b9a6d68e8db607db91842
https://github.com/qemu/qemu/commit/5601e6217d90ed322b4b9a6d68e8db607db91842
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 96631327be14c4f54cc31f873c278d9ffedd1e00
https://github.com/qemu/qemu/commit/96631327be14c4f54cc31f873c278d9ffedd1e00
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
The Linux kernel traps certain reserved instruction exceptions to
emulate the corresponding instructions. QEMU plays the role of the
kernel in user mode, so those traps are emulated by accepting the
instructions.
This change adds the function check_insn_opc_user_only to signal a
reserved instruction exception for flagged CPUs in QEMU system mode.
The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not
implemented in R5900 hardware. They are trapped and emulated by the
Linux kernel and, accordingly, therefore QEMU user only instructions.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 9d35580a577ceac602d6a5bc9a7368196f381855
https://github.com/qemu/qemu/commit/9d35580a577ceac602d6a5bc9a7368196f381855
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
A tests/tcg/mips/mipsr5900/Makefile
A tests/tcg/mips/mipsr5900/mult.c
Log Message:
-----------
tests/tcg/mips: Add tests for R5900 three-operand MULT
Add a test for MULT.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 667eded27024618422ca7e530d6dd4902fedc49f
https://github.com/qemu/qemu/commit/667eded27024618422ca7e530d6dd4902fedc49f
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M tests/tcg/mips/mipsr5900/Makefile
A tests/tcg/mips/mipsr5900/multu.c
Log Message:
-----------
tests/tcg/mips: Add tests for R5900 three-operand MULTU
Add a test for MULTU.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: cb56125eea7710a84703a3d274c7bcc38f180175
https://github.com/qemu/qemu/commit/cb56125eea7710a84703a3d274c7bcc38f180175
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M tests/tcg/mips/mipsr5900/mult.c
Log Message:
-----------
tests/tcg/mips: Add tests for R5900 three-operand MULT1
Add a test for MULT1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: bec4d66b2488c58e36554c70466c0e09d99c0888
https://github.com/qemu/qemu/commit/bec4d66b2488c58e36554c70466c0e09d99c0888
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M tests/tcg/mips/mipsr5900/multu.c
Log Message:
-----------
tests/tcg/mips: Add tests for R5900 three-operand MULTU1
Add a test for MULTU1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 3303f017adb4b4a10f907552995973a26d128a8d
https://github.com/qemu/qemu/commit/3303f017adb4b4a10f907552995973a26d128a8d
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M tests/tcg/mips/mipsr5900/Makefile
A tests/tcg/mips/mipsr5900/mflohi1.c
Log Message:
-----------
tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1
Add a test for MFLO1 and MFHI1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 4d261a6a595ef3f6d6f65d03927187b43a97e3f2
https://github.com/qemu/qemu/commit/4d261a6a595ef3f6d6f65d03927187b43a97e3f2
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M tests/tcg/mips/mipsr5900/Makefile
A tests/tcg/mips/mipsr5900/mtlohi1.c
Log Message:
-----------
tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1
Add a test for MTLO1 and MTHI1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 990aa328be42b27b78fcd40c6402971c3c49aac4
https://github.com/qemu/qemu/commit/990aa328be42b27b78fcd40c6402971c3c49aac4
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M tests/tcg/mips/mipsr5900/Makefile
A tests/tcg/mips/mipsr5900/div1.c
Log Message:
-----------
tests/tcg/mips: Add tests for R5900 DIV1
Add a test for DIV1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 35eb9be6bb637ad156a4e51e9f1cdbb8ed8496d4
https://github.com/qemu/qemu/commit/35eb9be6bb637ad156a4e51e9f1cdbb8ed8496d4
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M tests/tcg/mips/mipsr5900/Makefile
A tests/tcg/mips/mipsr5900/divu1.c
Log Message:
-----------
tests/tcg/mips: Add tests for R5900 DIVU1
Add a test for DIVU1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: ed4f49ba9bb56ebca6987b1083255daf6c89b5de
https://github.com/qemu/qemu/commit/ed4f49ba9bb56ebca6987b1083255daf6c89b5de
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate_init.inc.c
Log Message:
-----------
target/mips: Define the R5900 CPU
The primary purpose of this change is to support programs compiled by
GCC for the R5900 target and thereby run R5900 Linux distributions, for
example Gentoo.
GCC in version 7.3, by itself, by inspection of the GCC source code
and inspection of the generated machine code, for the R5900 target,
only emits two instructions that are specific to the R5900: the three-
operand MULT and MULTU. GCC and libc also emit certain MIPS III
instructions that are not part of the R5900 ISA. They are normally
trapped and emulated by the Linux kernel, and therefore need to be
treated accordingly by QEMU.
A program compiled by GCC is taken to mean source code compiled by GCC
under the restrictions above. One can, with the apparent limitations,
with a bit of effort obtain a fully functioning operating system such
as R5900 Gentoo. Strictly speaking, programs need not be compiled by
GCC to make use of this change.
Instructions and other facilities of the R5900 not implemented by this
change are intended to signal provisional exceptions. One such example
is the FPU that is not compliant with IEEE 754-1985 in system mode. It
is therefore provisionally disabled. In user space the FPU is trapped
and emulated by IEEE 754-1985 compliant software in the kernel, and
this is handled accordingly by QEMU. Another example is the 93
multimedia instructions specific to the R5900 that generate provisional
reserved instruction exception signals.
One of the benefits of running a Linux distribution under QEMU is that
programs can be compiled with a native compiler, where the host and
target are the same, as opposed to a cross-compiler, where they are
not the same. This is especially important in cases where the target
hardware does not have the resources to run a native compiler.
Problems with cross-compilation are often related to host and target
differences in integer sizes, pointer sizes, endianness, machine code,
ABI, etc. Sometimes cross-compilation is not even supported by the
build script for a given package. One effective way to avoid those
problems is to replace the cross-compiler with a native compiler. This
change of compilation methods does not resolve the inherent problems
with cross-compilation.
The native compiler naturally replaces the cross-compiler, because one
typically uses one or the other, and preferably the native compiler
when the circumstances admit this. The native compiler is also a good
test case for the R5900 QEMU user mode. Additionally, Gentoo is well-
known for compiling and installing its packages from sources.
This change has been tested with Gentoo compiled for R5900, including
native compilation of several packages under QEMU.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 4d9e5a0eb7df6e98ac6cf5e16029f35dd05b9537
https://github.com/qemu/qemu/commit/4d9e5a0eb7df6e98ac6cf5e16029f35dd05b9537
Author: Fredrik Noring <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M linux-user/mips/target_elf.h
Log Message:
-----------
linux-user/mips: Recognize the R5900 CPU model
This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU.
The R5900 FPU hardware is noncompliant and it is therefore emulated in
software by the Linux kernel. QEMU emulates a compliant FPU accordingly.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: ab99e0e44bc7b0e2e52d9083a673866b18470536
https://github.com/qemu/qemu/commit/ab99e0e44bc7b0e2e52d9083a673866b18470536
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Fix the title of translate.c
Replace MIPS32 with MIPS, since the file covers all generations
of MIPS architectures.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 373ecd3823f949fd550ec49685299e287af5753e
https://github.com/qemu/qemu/commit/373ecd3823f949fd550ec49685299e287af5753e
Author: Aleksandar Markovic <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Fix decoding of ALIGN and DALIGN instructions
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to
allow paremeter 'bp' to occupy two and three bits, respectively.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: c96292036a17857d62b8b5d3c8752bac3d6b7193
https://github.com/qemu/qemu/commit/c96292036a17857d62b8b5d3c8752bac3d6b7193
Author: Peter Maydell <address@hidden>
Date: 2018-10-24 (Wed, 24 Oct 2018)
Changed paths:
M linux-user/mips/target_elf.h
M target/mips/mips-defs.h
M target/mips/translate.c
M target/mips/translate_init.inc.c
A tests/tcg/mips/mipsr5900/Makefile
A tests/tcg/mips/mipsr5900/div1.c
A tests/tcg/mips/mipsr5900/divu1.c
A tests/tcg/mips/mipsr5900/mflohi1.c
A tests/tcg/mips/mipsr5900/mtlohi1.c
A tests/tcg/mips/mipsr5900/mult.c
A tests/tcg/mips/mipsr5900/multu.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2' into staging
MIPS queue for October 2018 - part 2 - v2
# gpg: Signature made Wed 24 Oct 2018 14:22:54 BST
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2: (33 commits)
target/mips: Fix decoding of ALIGN and DALIGN instructions
target/mips: Fix the title of translate.c
linux-user/mips: Recognize the R5900 CPU model
target/mips: Define the R5900 CPU
tests/tcg/mips: Add tests for R5900 DIVU1
tests/tcg/mips: Add tests for R5900 DIV1
tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1
tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1
tests/tcg/mips: Add tests for R5900 three-operand MULTU1
tests/tcg/mips: Add tests for R5900 three-operand MULT1
tests/tcg/mips: Add tests for R5900 three-operand MULTU
tests/tcg/mips: Add tests for R5900 three-operand MULT
target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
target/mips: Support R5900 DIV1 and DIVU1 instructions
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
target/mips: Support R5900 three-operand MULT and MULTU instructions
target/mips: Add a placeholder for R5900 MMI3 instruction subclass
target/mips: Add a placeholder for R5900 MMI2 instruction subclass
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/18e195645aa3...c96292036a17
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