[Qemu-commits] [qemu/qemu] 416756: Record history of ppcemb target in common.json

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 416756cc049006ab8a05fe39e5f2e6af25cad9d2
      
https://github.com/qemu/qemu/commit/416756cc049006ab8a05fe39e5f2e6af25cad9d2
  Author: Thomas Huth <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M qapi/common.json

  Log Message:
  -----------
  Record history of ppcemb target in common.json

We recently removed the long deprecated "ppcemb" target.  This adds a
comment in common.json about the SysEmuTarget type, recording when it was
removed.

Suggested-by: Eric Blake <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9545f2e10997155aa28b1fc229302cf4e8608c9b
      
https://github.com/qemu/qemu/commit/9545f2e10997155aa28b1fc229302cf4e8608c9b
  Author: Thomas Huth <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M target/ppc/cpu-models.c

  Log Message:
  -----------
  target/ppc/cpu-models: Re-group the 970 CPUs together again

The addition of the POWER9 CPUs divided the entries for the 970 CPUs,
which is a little bit confusing when you look at the code. So let's
re-group the 970 CPUs together again, and since these chips have been
based on the POWER4 processor, move them also in front of the POWER5
chips now.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8e93b2c3930b635032739ed3d944f72ac2ae6355
      
https://github.com/qemu/qemu/commit/8e93b2c3930b635032739ed3d944f72ac2ae6355
  Author: Hervé Poussineau <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/ppc/prep.c
    M tests/boot-serial-test.c

  Log Message:
  -----------
  hw/ppc: on 40p machine, change default firmware to OpenBIOS

OpenBIOS gained 40p support in 5b20e4cacecb62fb2bdc6867c11d44cddd77c4ff
Use it, instead of relying on an unmaintained and very limited firmware.

Signed-off-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 55a2290254192d828b9464acb175fb0dc24c7035
      
https://github.com/qemu/qemu/commit/55a2290254192d828b9464acb175fb0dc24c7035
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/pci-host/prep.c

  Log Message:
  -----------
  raven: some minor IRQ-related tidy-ups

This really lays the groundwork for the upcoming patches: it renames the
irqs PREPPCIState struct member to pci_irqs (as soon there will be a
distinction) and then changes the raven IRQ opaque to use PREPPCIState
instead of just irqs array.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f40b83a4e31ae1b56ae5494cf7dc8b015975ac4a
      
https://github.com/qemu/qemu/commit/f40b83a4e31ae1b56ae5494cf7dc8b015975ac4a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/pci-host/prep.c
    M hw/ppc/prep.c

  Log Message:
  -----------
  40p: use OR gate to wire up raven PCI interrupts

According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.

Instead of mapping each PCI IRQ separately, we introduce an OR gate within the
raven PCI host bridge and then wire the single output of the OR gate to the
interrupt controller.

Note that whilst the (now deprecated) PReP machine still exists we still need
to preserve the old IRQ routing. This is done by adding a new "is-legacy-prep"
property to the raven PCI host bridge which is set to true for the PReP
machine.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e39de895f6adc3a274f3116d4f38845d8fcbf135
      
https://github.com/qemu/qemu/commit/e39de895f6adc3a274f3116d4f38845d8fcbf135
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/ppc/spapr_irq.c
    M hw/ppc/spapr_pci.c
    M include/hw/ppc/spapr_irq.h
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  spapr: introduce a spapr_irq class 'nr_msis' attribute

The number of MSI interrupts a sPAPR machine can allocate is in direct
relation with the number of interrupts of the sPAPRIrq backend. Define
statically this value at the sPAPRIrq class level and use it for the
"ibm,pe-total-#msi" property of the sPAPR PHB.

According to the PAPR specs, "ibm,pe-total-#msi" defines the maximum
number of MSIs that are available to the PE. We choose to advertise
the maximum number of MSIs that are available to the machine for
simplicity of the model and to avoid segmenting the MSI interrupt pool
which can be easily shared. If the pool limit is reached, it can be
extended dynamically.

Finally, remove XICS_IRQS_SPAPR which is now unused.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ae837402379b649e942b6a968de88b94585a5c84
      
https://github.com/qemu/qemu/commit/ae837402379b649e942b6a968de88b94585a5c84
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_irq.c
    M include/hw/ppc/spapr_irq.h

  Log Message:
  -----------
  spapr: increase the size of the IRQ number space

The new layout using static IRQ number does not leave much space to
the dynamic MSI range, only 0x100 IRQ numbers. Increase the total
number of IRQS for newer machines and introduce a legacy XICS backend
for pre-3.1 machines to maintain compatibility.

For the old backend, provide a 'nr_msis' value covering the full IRQ
number space as it does not use the bitmap allocator to allocate MSI
interrupt numbers.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0976efd51bbfb28292704a248cb9454fc12f911d
      
https://github.com/qemu/qemu/commit/0976efd51bbfb28292704a248cb9454fc12f911d
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h

  Log Message:
  -----------
  spapr_pci: add an extra 'nr_msis' argument to spapr_populate_pci_dt

So that we don't have to call qdev_get_machine() to get the machine
class and the sPAPRIrq backend holding the number of MSIs.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f3a60058c97f2f923e3883a8b129c7c8dfe46a3a
      
https://github.com/qemu/qemu/commit/f3a60058c97f2f923e3883a8b129c7c8dfe46a3a
  Author: Marcus Comstedt <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/display/sm501.c

  Log Message:
  -----------
  sm501: Adjust endianness of pixel value in rectangle fill

The value from twoD_foreground (which is in host endian format) must
be converted to the endianness of the framebuffer (currently always
little endian) before it can be used to perform the fill operation.

Signed-off-by: Marcus Comstedt <address@hidden>
Reviewed-by: BALATON Zoltan <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f74a4f3a59b6168b8f3e84e4276c47eda610891d
      
https://github.com/qemu/qemu/commit/f74a4f3a59b6168b8f3e84e4276c47eda610891d
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/scsi/lsi53c895a.c
    M include/hw/pci/pci.h

  Log Message:
  -----------
  scsi: add lsi53c8xx_handle_legacy_cmdline() function

This is the function that will soon be used to replace lsi53c895a_create() and
lsi53c810_create().

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 877eb21d5607e5097b8331e7a5b3d9714c0c5b91
      
https://github.com/qemu/qemu/commit/877eb21d5607e5097b8331e7a5b3d9714c0c5b91
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/realview.c
    M hw/arm/versatilepb.c
    M hw/hppa/machine.c
    M hw/ppc/prep.c

  Log Message:
  -----------
  scsi: move lsi53c8xx_create() callers to lsi53c8xx_handle_legacy_cmdline()

As part of commits a64aa5785d "hw: Deprecate -drive if=scsi with non-onboard
HBAs" and b891538e81 "hw/ppc/prep: Fix implicit creation of "-drive if=scsi"
devices" the lsi53c895a_create() and lsi53c810_create() functions were added
to wrap pci_create_simple() and scsi_bus_legacy_handle_cmdline().

Unfortunately this prevents us from changing qdev properties on the device
and/or changing the PCI configuration. By switching over to using the new
lsi53c8xx_handle_legacy_cmdline() function then the caller can now configure
and realize the LSI SCSI device exactly as required.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Peter Maydell <address@hidden> [arm parts]
Signed-off-by: David Gibson <address@hidden>


  Commit: e090a054a7c1d8cada034a362d05b2a8fee3a420
      
https://github.com/qemu/qemu/commit/e090a054a7c1d8cada034a362d05b2a8fee3a420
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/scsi/lsi53c895a.c
    M include/hw/pci/pci.h

  Log Message:
  -----------
  scsi: remove unused lsi53c895a_create() and lsi53c810_create() functions

Now that these functions are no longer required they can be removed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3cc1b9cba915c4adfa73d68e344677574a5a5267
      
https://github.com/qemu/qemu/commit/3cc1b9cba915c4adfa73d68e344677574a5a5267
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/scsi/lsi53c895a.c

  Log Message:
  -----------
  lsi53c895a: add optional external IRQ via qdev

On some early machines the on-board PCI devices IRQs are wired directly to
the interrupt controller instead of via the PCI host bridge.

Add an optional external IRQ that if wired up via qdev will replace the
in-built PCI IRQ.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Fam Zheng <address@hidden>
Reviewed-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0358687b16407670f09649dfdc079c04a3522493
      
https://github.com/qemu/qemu/commit/0358687b16407670f09649dfdc079c04a3522493
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/ppc/prep.c

  Log Message:
  -----------
  40p: add fixed IRQ routing for LSI SCSI device

Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
15 on the interrupt controller, the real 40p machine has a routing quirk in
that the LSI SCSI device is routed directly to IRQ 13.

Enable the external IRQ for the LSI SCSI device by wiring up the IRQ with
qdev to the relevant interrupt controller gpio.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Acked-by: David Gibson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 506e4a00de01e0b29fa83db5cbbc3d154253b4ea
      
https://github.com/qemu/qemu/commit/506e4a00de01e0b29fa83db5cbbc3d154253b4ea
  Author: Peter Maydell <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/realview.c
    M hw/arm/versatilepb.c
    M hw/display/sm501.c
    M hw/hppa/machine.c
    M hw/pci-host/prep.c
    M hw/ppc/prep.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_irq.c
    M hw/ppc/spapr_pci.c
    M hw/scsi/lsi53c895a.c
    M include/hw/pci-host/spapr.h
    M include/hw/pci/pci.h
    M include/hw/ppc/spapr_irq.h
    M include/hw/ppc/xics.h
    M qapi/common.json
    M target/ppc/cpu-models.c
    M tests/boot-serial-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into 
staging

ppc patch queue 2018-09-25

Here are the accumulated ppc target patches for the last several
weeks. Highlights are:
   * A number of 40p / PReP cleanups
   * Preliminary irq rework on the pseries machine towards the new
     XIVE interrupt controller

There are a few patches which make small changes to generic device and
arm code as prerequisites to the 40p interrupt routing cleanup.  They
have acks from the relevant maintainers.

# gpg: Signature made Tue 25 Sep 2018 08:00:06 BST
# gpg:                using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-3.1-20180925:
  40p: add fixed IRQ routing for LSI SCSI device
  lsi53c895a: add optional external IRQ via qdev
  scsi: remove unused lsi53c895a_create() and lsi53c810_create() functions
  scsi: move lsi53c8xx_create() callers to lsi53c8xx_handle_legacy_cmdline()
  scsi: add lsi53c8xx_handle_legacy_cmdline() function
  sm501: Adjust endianness of pixel value in rectangle fill
  spapr_pci: add an extra 'nr_msis' argument to spapr_populate_pci_dt
  spapr: increase the size of the IRQ number space
  spapr: introduce a spapr_irq class 'nr_msis' attribute
  40p: use OR gate to wire up raven PCI interrupts
  raven: some minor IRQ-related tidy-ups
  hw/ppc: on 40p machine, change default firmware to OpenBIOS
  target/ppc/cpu-models: Re-group the 970 CPUs together again
  Record history of ppcemb target in common.json

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/32556acb5a02...506e4a00de01
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