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[Qemu-commits] [qemu/qemu] e79b44: target/arm: Fix cpu_get_tb_cpu_state(


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] e79b44: target/arm: Fix cpu_get_tb_cpu_state() for non-SVE...
Date: Tue, 25 Sep 2018 07:48:37 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e79b445d896deb61909be52b61b87c98a9ed96f7
      
https://github.com/qemu/qemu/commit/e79b445d896deb61909be52b61b87c98a9ed96f7
  Author: Richard Henderson <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs

Not only are the sve-related tb_flags fields unused when SVE is
disabled, but not all of the cpu registers are initialized properly
for computing same.  This can corrupt other fields by ORing in -1,
which might result in QEMU crashing.

This bug was not present in 3.0, but this patch is cc'd to
stable because adf92eab90e3f5f34c285 where the bug was
introduced was marked for stable.

Fixes: adf92eab90e3f5f34c285
Cc: address@hidden (3.0.1)
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5561adf062c97a9c39ff037592b83d9b118f036a
      
https://github.com/qemu/qemu/commit/5561adf062c97a9c39ff037592b83d9b118f036a
  Author: Bartlomiej Zolnierkiewicz <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/exynos4210.c

  Log Message:
  -----------
  hw/arm/exynos4210: fix Exynos4210 UART support

commit 97274d0c05d4 ("hw/char/exynos4210_uart.c: Remove unneeded
handling of NULL chardev") broke Exynos4210 support as it removed
NULL 'Chardev *chr' handling from exynos4210_uart_create() and
currently exynos4210_init() always passes NULL as 'Chardev *chr'
argument to exynos4210_uart_create() calls. Fix it by adding
missing serial_hd() calls to exynos4210_init().

Signed-off-by: Bartlomiej Zolnierkiewicz <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 66c353cea6c06c64fc68d1f663fdfdca55d4e421
      
https://github.com/qemu/qemu/commit/66c353cea6c06c64fc68d1f663fdfdca55d4e421
  Author: Shannon Zhao <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes

Like commit 16b4226(hw/acpi-build: Add a check for memory-less NUMA node
), it also needs to check memory length for NUMA nodes on ARM.

Signed-off-by: Shannon Zhao <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c0066d1a1900e8f44a004c588257116c25bbde55
      
https://github.com/qemu/qemu/commit/c0066d1a1900e8f44a004c588257116c25bbde55
  Author: Joel Stanley <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add NRF51 entry

This contains the NRF51, and the machine that uses it, the BBC
micro:bit.

Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 673b2d42a8bfbc36bbfd9aad18410b3970913043
      
https://github.com/qemu/qemu/commit/673b2d42a8bfbc36bbfd9aad18410b3970913043
  Author: Joel Stanley <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/nrf51_soc.c
    A include/hw/arm/nrf51_soc.h

  Log Message:
  -----------
  arm: Add Nordic Semiconductor nRF51 SoC

The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
plus other common ARM SoC peripherals.

 http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf

This defines a basic model of the CPU and memory, with no peripherals
implemented at this stage.

Signed-off-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: wrapped a few long lines]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b148ed466514c8b50e7cf6fb45985a1ab98db1f8
      
https://github.com/qemu/qemu/commit/b148ed466514c8b50e7cf6fb45985a1ab98db1f8
  Author: Joel Stanley <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/microbit.c

  Log Message:
  -----------
  arm: Add BBC micro:bit machine

This adds the base for a machine model of the BBC micro:bit:

  https://en.wikipedia.org/wiki/Micro_Bit

This is a system with a nRF51 SoC containing the main processor, with
various peripherals on board.

Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5540cb97f711d191bae6cde89a03a8a9c306b638
      
https://github.com/qemu/qemu/commit/5540cb97f711d191bae6cde89a03a8a9c306b638
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/i2c/aspeed_i2c.c

  Log Message:
  -----------
  aspeed/i2c: interrupts should be cleared by software only

aspeed i2c interrupts should be cleared by software only, and the bus
interrupt should be lowered when all interrupts have been cleared.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: drop TODO comment describing an issue which is
 fixed later in the patch series, and clean up commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7bd9c60d4e0d113a8a4428bcbddc5aa9d41d1edc
      
https://github.com/qemu/qemu/commit/7bd9c60d4e0d113a8a4428bcbddc5aa9d41d1edc
  Author: Guenter Roeck <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/i2c/aspeed_i2c.c

  Log Message:
  -----------
  aspeed/i2c: Handle receive command in separate function

Receive command handling may have to be deferred if a previous receive
done interrupt was not yet acknowledged. Move receive command handling
into a separate function to prepare for the necessary changes.

Signed-off-by: Guenter Roeck <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bb626e5b43df996a19b53cb6033b25d83f7b2e73
      
https://github.com/qemu/qemu/commit/bb626e5b43df996a19b53cb6033b25d83f7b2e73
  Author: Guenter Roeck <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/i2c/aspeed_i2c.c

  Log Message:
  -----------
  aspeed/i2c: Fix receive done interrupt handling

The AST2500 datasheet says:

I2CD10 Interrupt Status Register
       bit 2 Receive Done Interrupt status
       S/W needs to clear this status bit to allow next data receiving

The Rx interrupt done interrupt status bit needs to be cleared
explicitly before the next byte can be received, and must therefore
not be auto-cleared. Also, receiving the next byte must be delayed
until the bit has been cleared.

Signed-off-by: Guenter Roeck <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6ce9297be69be10465b556a4b3380f70634c16a7
      
https://github.com/qemu/qemu/commit/6ce9297be69be10465b556a4b3380f70634c16a7
  Author: Eric Auger <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/smmu-common.c

  Log Message:
  -----------
  hw/arm/smmu-common: Fix the name of the iommu memory regions

At the point smmu_find_add_as() gets called, the bus number might
not be computed. Let's change the name of IOMMU memory region and
just use the devfn and an incrementing index.

The name only is used for debug.

Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: changed 'uint' to 'unsigned int']
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9f4d2a1316fc294da5c0646fa93894d5f5f0c9a0
      
https://github.com/qemu/qemu/commit/9f4d2a1316fc294da5c0646fa93894d5f5f0c9a0
  Author: Eric Auger <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c

  Log Message:
  -----------
  hw/arm/smmuv3: fix eventq recording and IRQ triggerring

The event queue management is broken today. Event records
are not properly written as EVT_SET_* macro was not updating
the actual event record. Also the event queue interrupt
is not correctly triggered.

Fixes: bb981004eaf4 ("hw/arm/smmuv3: Event queue recording helper")
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 48314d831679373edb13712ff4a1abcb1937a0bd
      
https://github.com/qemu/qemu/commit/48314d831679373edb13712ff4a1abcb1937a0bd
  Author: Peter Maydell <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M include/hw/intc/arm_gic.h

  Log Message:
  -----------
  hw/intc/arm_gic: Document QEMU interface

The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
etc) is now quite complicated with the addition of the
virtualization extensions. Add a comment in the header
file which documents it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: b6e6c65151efb72063a9dd62fbd5baa744d4ab30
      
https://github.com/qemu/qemu/commit/b6e6c65151efb72063a9dd62fbd5baa744d4ab30
  Author: Peter Maydell <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/gic_internal.h

  Log Message:
  -----------
  hw/intc/arm_gic: Drop GIC_BASE_IRQ macro

The GIC_BASE_IRQ macro is a leftover from when we shared code
between the GICv2 and the v7M NVIC. Since the NVIC is now
split off, GIC_BASE_IRQ is always 0, and we can just delete it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: 5d026de8b6aeb4d494c21ac32112c2821bd05422
      
https://github.com/qemu/qemu/commit/5d026de8b6aeb4d494c21ac32112c2821bd05422
  Author: Peter Maydell <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/net/pcnet-pci.c
    M hw/net/trace-events

  Log Message:
  -----------
  hw/net/pcnet-pci: Convert away from old_mmio accessors

Convert the pcnet-pci device away from using the old_mmio
MemoryRegionOps accessor functions.

This commit is a no-behaviour-change API conversion.
(Since PCNET_PNPMMIO_SIZE is 0x20, the old "addr & 0x10"
check and the new "addr < 0x10" check are exact opposites;
the new code is phrased to be parallel with the
pcnet_io_read/write functions.)

I have left a TODO comment marker because the similarity
between the MMIO and IO accessor behaviour is suspicious
and they could be combined, but this will be left to a
different patch.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b187e20f9b902b611ca9288cef5c490cbb2d91dd
      
https://github.com/qemu/qemu/commit/b187e20f9b902b611ca9288cef5c490cbb2d91dd
  Author: Peter Maydell <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/net/pcnet-pci.c
    M hw/net/trace-events

  Log Message:
  -----------
  hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write

The only difference between our implementation of the pcnet ioport
accessors and the mmio accessors is that the former check BCR_DWIO to
see what access widths are permitted for addresses in the aprom range
(0x0..0xf). In fact our failure to do this in the mmio accessors
is a bug (one which was fixed for the ioport accessors in
commit 7ba79741970 in 2011).

The data sheet for the Am79C970A does not describe the DWIO
bit as only applying for I/O space mapped I/O resources and
not memory mapped I/O resources, and our MMIO accessors already
honour DWIO for accesses in the 0x10..0x1f range (since the
pcnet_ioport_{read,write}{w,l} functions check it).

The data sheet for the later but compatible Am79C976 is clearer:
it states specifically "DWIO mode applies to both I/O- and
memory-mapped acceses." This seems to be reasonable evidence
in favour of interpretating the Am79C970A spec as being the same.

(NB: Linux's pcnet driver only supports I/O accesses, so the
MMIO access part of this device is probably untested anyway.)

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3e1dd459cbd95c66753f7c9368e680dde2ba60e2
      
https://github.com/qemu/qemu/commit/3e1dd459cbd95c66753f7c9368e680dde2ba60e2
  Author: Peter Maydell <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/timer/cmsdk-apb-dualtimer.c

  Log Message:
  -----------
  hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements

Add 'break' statements missing from a switch in the APB dual-timer
write function. Spotted by Coverity as CID 1395626 and 1395633.

Reported-by: Paolo Bonzini <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 03f1d7201a8ac6adeb3aae8c575f3e67e153c54a
      
https://github.com/qemu/qemu/commit/03f1d7201a8ac6adeb3aae8c575f3e67e153c54a
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/timer/aspeed_timer.c
    M include/hw/timer/aspeed_timer.h

  Log Message:
  -----------
  aspeed/timer: fix compile breakage with clang 3.4.2

In file included from /home/thuth/devel/qemu/hw/timer/aspeed_timer.c:16:
/home/thuth/devel/qemu/include/hw/misc/aspeed_scu.h:37:3: error:
redefinition of typedef 'AspeedSCUState' is a C11 feature
      [-Werror,-Wtypedef-redefinition]
} AspeedSCUState;
  ^
/home/thuth/devel/qemu/include/hw/timer/aspeed_timer.h:27:31: note:
previous definition is here
typedef struct AspeedSCUState AspeedSCUState;

Reported-by: Thomas Huth <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3d9bada2408329269424628a3be6340c6c28de0e
      
https://github.com/qemu/qemu/commit/3d9bada2408329269424628a3be6340c6c28de0e
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw/arm/aspeed: change the FMC flash model of the AST2500 evb

The AST2500 evb is shipped with a W25Q256 which has a non volatile bit
to make the chip operate in 4 Byte address mode at power up. This
should be an interesting feature to model as it will exercise a bit
more the SMC controllers and MMIO execution at boot time.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fca9ca1b13593ba23b924ac79212753a43d825d3
      
https://github.com/qemu/qemu/commit/fca9ca1b13593ba23b924ac79212753a43d825d3
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/arm/aspeed.c
    A include/hw/arm/aspeed.h

  Log Message:
  -----------
  hw/arm/aspeed: Add an Aspeed machine class

The code looks better, it removes duplicated lines and it will ease
the introduction of common properties for the Aspeed machines.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b3d6b8f5af62fcfcec53110388a46960e641c5b4
      
https://github.com/qemu/qemu/commit/b3d6b8f5af62fcfcec53110388a46960e641c5b4
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: fix some alignment issues

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf
      
https://github.com/qemu/qemu/commit/060a65df056a5d6ca3a6a91e7bf150ca1fbccddf
  Author: Peter Maydell <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode

The ARMv8 architecture defines that an AArch32 CPU starts
in SVC mode, unless EL2 is the highest available EL, in
which case it starts in Hyp mode. (In ARMv7 a CPU with EL2
but not EL3 was not a valid configuration, but we don't
specifically reject this if the user asks for one.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 71fbecea0f725bc16aec32cf89cbf3aa78058826
      
https://github.com/qemu/qemu/commit/71fbecea0f725bc16aec32cf89cbf3aa78058826
  Author: Peter Maydell <address@hidden>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    M hw/arm/aspeed.c
    M hw/arm/exynos4210.c
    A hw/arm/microbit.c
    A hw/arm/nrf51_soc.c
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/virt-acpi-build.c
    M hw/i2c/aspeed_i2c.c
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/gic_internal.h
    M hw/net/pcnet-pci.c
    M hw/net/trace-events
    M hw/ssi/aspeed_smc.c
    M hw/timer/aspeed_timer.c
    M hw/timer/cmsdk-apb-dualtimer.c
    A include/hw/arm/aspeed.h
    A include/hw/arm/nrf51_soc.h
    M include/hw/intc/arm_gic.h
    M include/hw/timer/aspeed_timer.h
    M target/arm/cpu.c
    M target/arm/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20180925-1' into staging

target-arm queue:
 * target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
 * hw/arm/exynos4210: fix Exynos4210 UART support
 * hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
 * arm: Add BBC micro:bit machine
 * aspeed/i2c: Fix interrupt handling bugs
 * hw/arm/smmu-common: Fix the name of the iommu memory regions
 * hw/arm/smmuv3: fix eventq recording and IRQ triggerring
 * hw/intc/arm_gic: Document QEMU interface
 * hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
 * hw/net/pcnet-pci: Convert away from old_mmio accessors
 * hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
 * aspeed/timer: fix compile breakage with clang 3.4.2
 * hw/arm/aspeed: change the FMC flash model of the AST2500 evb
 * hw/arm/aspeed: Minor code cleanups
 * target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode

# gpg: Signature made Tue 25 Sep 2018 15:23:11 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180925-1: (21 commits)
  target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
  aspeed/smc: fix some alignment issues
  hw/arm/aspeed: Add an Aspeed machine class
  hw/arm/aspeed: change the FMC flash model of the AST2500 evb
  aspeed/timer: fix compile breakage with clang 3.4.2
  hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
  hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write
  hw/net/pcnet-pci: Convert away from old_mmio accessors
  hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
  hw/intc/arm_gic: Document QEMU interface
  hw/arm/smmuv3: fix eventq recording and IRQ triggerring
  hw/arm/smmu-common: Fix the name of the iommu memory regions
  aspeed/i2c: Fix receive done interrupt handling
  aspeed/i2c: Handle receive command in separate function
  aspeed/i2c: interrupts should be cleared by software only
  arm: Add BBC micro:bit machine
  arm: Add Nordic Semiconductor nRF51 SoC
  MAINTAINERS: Add NRF51 entry
  hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
  hw/arm/exynos4210: fix Exynos4210 UART support
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/506e4a00de01...71fbecea0f72
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      Functionality will be removed from GitHub.com on January 31st, 2019.

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