[Qemu-commits] [qemu/qemu] d10302: tcg: Document INDEX_mul[us]h_*

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d103021269ca9307ed7ca0d845d2b9e6c387509a
      
https://github.com/qemu/qemu/commit/d103021269ca9307ed7ca0d845d2b9e6c387509a
  Author: Richard Henderson <address@hidden>
  Date:   2018-05-01 (Tue, 01 May 2018)

  Changed paths:
    M tcg/README

  Log Message:
  -----------
  tcg: Document INDEX_mul[us]h_*

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 3f814b803797c007abfe5c4041de754e01723031
      
https://github.com/qemu/qemu/commit/3f814b803797c007abfe5c4041de754e01723031
  Author: Henry Wertz <address@hidden>
  Date:   2018-05-01 (Tue, 01 May 2018)

  Changed paths:
    M tcg/arm/tcg-target.inc.c

  Log Message:
  -----------
  tcg/arm: Fix memory barrier encoding

I found with qemu 2.11.x or newer that I would get an illegal instruction
error running some Intel binaries on my ARM chromebook.  On investigation,
I found it was quitting on memory barriers.

qemu instruction:
mb $0x31
was translating as:
0x604050cc:  5bf07ff5  blpl     #0x600250a8

After patch it gives:
0x604050cc:  f57ff05b  dmb      ish

In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be
correct based on online docs, but due to some endian-related shenanigans it
had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory
barrier for ARMv6) also should be byte swapped  (and this patch does so).
I have not checked for correctness of aarch64's barrier instruction.

Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Henry Wertz <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9a938d86b04025ac605db0ea9819e5896bf576ec
      
https://github.com/qemu/qemu/commit/9a938d86b04025ac605db0ea9819e5896bf576ec
  Author: Richard Henderson <address@hidden>
  Date:   2018-05-01 (Tue, 01 May 2018)

  Changed paths:
    M tcg/tcg-op-vec.c

  Log Message:
  -----------
  tcg: Allow wider vectors for cmp and mul

In db432672, we allow wide inputs for operations such as add.
However, in 212be173 and 3774030a we didn't do the same for
compare and multiply.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 5bfa803448638a45542441fd6b7cc1241403ea72
      
https://github.com/qemu/qemu/commit/5bfa803448638a45542441fd6b7cc1241403ea72
  Author: Richard Henderson <address@hidden>
  Date:   2018-05-01 (Tue, 01 May 2018)

  Changed paths:
    M target/hppa/translate.c
    M tcg/tcg-op.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Improve TCGv_ptr support

Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros.

Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr,
tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32.

Use inlines instead of macros where possible.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 6001f7729e12dd1d810291e4cbf83cee8e07441d
      
https://github.com/qemu/qemu/commit/6001f7729e12dd1d810291e4cbf83cee8e07441d
  Author: Laurent Vivier <address@hidden>
  Date:   2018-05-01 (Tue, 01 May 2018)

  Changed paths:
    M tcg/tcg-ldst.inc.c
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: workaround branch instruction overflow in tcg_out_qemu_ld/st

ppc64 uses a BC instruction to call the tcg_out_qemu_ld/st
slow path. BC instruction uses a relative address encoded
on 14 bits.

The slow path functions are added at the end of the generated
instructions buffer, in the reverse order of the callers.
So more we have slow path functions more the distance between
the caller (BC) and the function increases.

This patch changes the behavior to generate the functions in
the same order of the callers.

Cc: address@hidden
Fixes: 15fa08f845 ("tcg: Dynamically allocate TCGOps")
Signed-off-by: Laurent Vivier <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 59255887e6cafeff747250d2613003a41d1d9dff
      
https://github.com/qemu/qemu/commit/59255887e6cafeff747250d2613003a41d1d9dff
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-03 (Thu, 03 May 2018)

  Changed paths:
    M target/hppa/translate.c
    M tcg/README
    M tcg/arm/tcg-target.inc.c
    M tcg/tcg-ldst.inc.c
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180502' into staging

Queued TCG patches

# gpg: Signature made Wed 02 May 2018 18:43:33 BST
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <address@hidden>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20180502:
  tcg: workaround branch instruction overflow in tcg_out_qemu_ld/st
  tcg: Improve TCGv_ptr support
  tcg: Allow wider vectors for cmp and mul
  tcg/arm: Fix memory barrier encoding
  tcg: Document INDEX_mul[us]h_*

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/98bae9c4afb4...59255887e6ca
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