[Qemu-commits] [qemu/qemu] ee9a56: spapr_vio/spapr_iommu: Move VIO bypass where it be...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ee9a569ab88edd0755402aaf31ec0c69decf7756
      
https://github.com/qemu/qemu/commit/ee9a569ab88edd0755402aaf31ec0c69decf7756
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_vio.h

  Log Message:
  -----------
  spapr_vio/spapr_iommu: Move VIO bypass where it belongs

Instead of tweaking a TCE table device by adding there a bypass flag,
let's add an alias to RAM and IOMMU memory region, and enable/disable
those according to the selected bypass mode.
This way IOMMU memory region can have size of the actual window rather
than ram_size which is essential for upcoming DDW support.

This moves bypass logic to VIO layer and keeps @bypass flag in TCE table
for migration compatibility only. This replaces spapr_tce_set_bypass()
calls with explicit assignment to avoid confusion as the function could
do something more that just syncing the @bypass flag.

This adds a pointer to VIO device into the sPAPRTCETable struct to provide
the sPAPRTCETable device a way to update bypass mode for the VIO device.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ad3e67d05a65da2e3696ed45b999e061ccb7a879
      
https://github.com/qemu/qemu/commit/ad3e67d05a65da2e3696ed45b999e061ccb7a879
  Author: Aneesh Kumar K.V <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu-hash64.h

  Log Message:
  -----------
  target-ppc: Use right page size with hash table lookup

We look at two sizes specified in ISA (4K, 64K). If not found matching,
we consider it 16MB.

Without this patch we would fail to lookup address above 16MB range.
Below 16MB happened to work before because the kernel have a liner
mapping and we always looked up hash for 0xc000000000000000. The
actual real address was computed by using the 16MB offset
with the real address found with the above hash.

Without Fix:
(gdb) x/16x 0xc000000001000000
0xc000000001000000 <list_entries+453208>:       Cannot access memory at address 
0xc000000001000000
(gdb)

With Fix:
(gdb)  x/16x 0xc000000001000000
0xc000000001000000 <list_entries+453208>:       0x00000000      0x00000000      
0x00000000      0x00000000
0xc000000001000010 <list_entries+453224>:       0x00000000      0x00000000      
0x00000000      0x00000000
0xc000000001000020 <list_entries+453240>:       0x00000000      0x00000000      
0x00000000      0x00000000
0xc000000001000030 <list_entries+453256>:       0x00000000      0x00000000      
0x00000000      0x00000000

Signed-off-by: Aneesh Kumar K.V <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3e4ac9687103f907eadea10d6176eb2e989d1e36
      
https://github.com/qemu/qemu/commit/3e4ac9687103f907eadea10d6176eb2e989d1e36
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h

  Log Message:
  -----------
  pseries: Limit PCI host bridge "index" value

pseries guests can have large numbers of PCI host bridges.  To avoid the
user having to specify a number of different configuration values for every
one, the device supports an "index" property which is a shorthand setting
the various window and configuration addresses from a predefined sensible
set.

There are some problems with the details at present:
  * The "index" propery is signed, but negative values will create PCI
windows below where we expect, potentially colliding with other devices
  * No limit is imposed on the "index" property and large values can
translate to extremely large window addresses.  With PCI passthrough in
particular this can mean we exceed various mapping and physical address
limits causing the guest host bridge to not work in strange ways.

This patch addresses this, by making "index" unsigned, and imposing a
limit.  Currently the limit allows indices from 0..255 which is probably
enough host bridges for the time being.  It's fairly easy to extend if
we discover we need more.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3dab024430cf72ea65afce227585f9768fb3bfa7
      
https://github.com/qemu/qemu/commit/3dab024430cf72ea65afce227585f9768fb3bfa7
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Add pseries-2.3 machine

The next patch will make MMIO space bigger and keep the old value for
older pseries machines.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b194df478ae7607d93b47a8307e623c9f9f2b3ab
      
https://github.com/qemu/qemu/commit/b194df478ae7607d93b47a8307e623c9f9f2b3ab
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h

  Log Message:
  -----------
  spapr-pci: Enable huge BARs

At the moment sPAPR only supports 512MB window for MMIO BARs. However
modern devices might want bigger 64bit BARs.

This extends MMIO window from 512MB to 62GB (aligned to
SPAPR_PCI_WINDOW_SPACING) and advertises it in 2 records in
the PHB "ranges" property. 32bit gets the space from
SPAPR_PCI_MEM_WIN_BUS_OFFSET till the end of 4GB, 64bit gets the rest
of the space. If no space is left, 64bit range is not advertised.

The MMIO space size is set to old value of 0x20000000 by default
for pseries machines older than 2.3.

The approach changes the device tree which is a guest visible change, however
it won't break migration as:
1. we do not support migration to older QEMU versions
2. migration to newer QEMU will migrate the device tree as well and since
the new layout only extends the old one and does not change address mappigns,
no breakage is expected here too.

SLOF change is required to utilize this extension.

Suggested-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8e099d14f5233f330c4a6f03ff655219cd789c8f
      
https://github.com/qemu/qemu/commit/8e099d14f5233f330c4a6f03ff655219cd789c8f
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/timer/mc146818rtc.c
    M include/qom/object.h
    M qom/object.c

  Log Message:
  -----------
  Generalize QOM publishing of date and time from mc146818rtc.c

The mc146818rtc driver exposes the current RTC date and time via the "date"
property in QOM (which is also aliased to the machine's "rtc-time"
property).  Currently it uses a custom visitor function rtc_get_date to
do this.

This patch introduces new helpers to the QOM core to expose struct tm
valued properties via a getter function, so that this functionality can be
more easily duplicated in other RTC implementations.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 87774a4a4217b5cddc693f0678d0fc2bfc7f2ec1
      
https://github.com/qemu/qemu/commit/87774a4a4217b5cddc693f0678d0fc2bfc7f2ec1
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M include/migration/vmstate.h

  Log Message:
  -----------
  Add more VMSTATE_*_TEST variants for integers

Currently, vmstate.h includes helper macro variants for 8, 16 and 32-bit
unsigned integers which include a "test" function which can selectively
enable or disable the field's presence in the migration stream.

There aren't similar helpers for 64-bit unsigned integers, or any size of
signed integers.  This patch remedies this.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 12f421745cd763742377c7134f48fa12fb889ee3
      
https://github.com/qemu/qemu/commit/12f421745cd763742377c7134f48fa12fb889ee3
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/Makefile.objs
    M hw/ppc/spapr.c
    M hw/ppc/spapr_rtas.c
    A hw/ppc/spapr_rtc.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  pseries: Move sPAPR RTC code into its own file

At the moment the RTAS (firmware/hypervisor) time of day functions are
implemented in spapr_rtas.c along with a bunch of other things.  Since
we're going to be expanding these a bit, move the RTAS RTC related code
out into new file spapr_rtc.c.  Also add its own initialization function,
spapr_rtc_init() called from the main machine init routine.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: bbade20633a6b4ed7333e03a76038eda98950946
      
https://github.com/qemu/qemu/commit/bbade20633a6b4ed7333e03a76038eda98950946
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr_rtc.c

  Log Message:
  -----------
  pseries: Add more parameter validation in RTAS time of day functions

Currently, the RTAS time of day functions only partially validate the
number of parameters they receive and return.  Because of how the
parameters are used, this is unlikely to lead to a crash, but it's messy.

This patch adds the missing checks.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e5dad1d7d1618822dbadb1dd12efa1b5674b6c40
      
https://github.com/qemu/qemu/commit/e5dad1d7d1618822dbadb1dd12efa1b5674b6c40
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_rtc.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  pseries: Add spapr_rtc_read() helper function

The virtual RTC time is used in two places in the pseries machine.  First
is in the RTAS get-time-of-day function which returns the RTC time to the
guest.  Second is in the spapr events code which is used to timestamp
event messages from the hypervisor to the guest.

Currently both call qemu_get_timedate() directly, but we want to change
that so we can properly handle the various -rtc options.  In preparation,
create a helper function to return the virtual RTC time.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f01c5d84775cfc877dc0b537565a168d043394e9
      
https://github.com/qemu/qemu/commit/f01c5d84775cfc877dc0b537565a168d043394e9
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr_rtc.c

  Log Message:
  -----------
  pseries: Make RTAS time of day functions respect -rtc options

In the 'pseries' machine the real time clock is provided by a
paravirtualized firmware interface rather than a device per se; the RTAS
get-time-of-day and set-time-of-day calls.

Out current implementations of those work directly off host time (with
an offset), not respecting options such as clock=vm which can be
specified in the -rtc command line option.

This patch reworks the RTAS RTC code to respect those options, primarily
by basing them on the qemu_clock_get_ns(rtc_clock) function instead of
directly on qemu_get_timedate() (which essentially handles host time, not
virtual rtc time).

As a bonus, this means our get-time-of-day function now also returns
nanoseconds.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 28df36a13a3b0b792d9df64f8db8a392df5e0b35
      
https://github.com/qemu/qemu/commit/28df36a13a3b0b792d9df64f8db8a392df5e0b35
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_rtc.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  pseries: Make the PAPR RTC a qdev device

At present the PAPR RTC isn't a "device" as such - it's accessed only via
firmware/hypervisor calls, and is handled in the sPAPR core code.  This
becomes inconvenient as we extend it in various ways.

This patch makes the PAPR RTC a separate device in the qemu device model.

For now, the only piece of device state - the rtc_offset - is still kept in
the global sPAPREnvironment structure.  That's clearly wrong, but leaving
it to be fixed in a following patch makes for a clearer separation between
the internal re-organization of the device, and the behavioural changes
(because the migration stream format needs to change slightly when the
offset is moved into the device's own state).

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 880ae7de5958a765699386777de0f3841d635e1d
      
https://github.com/qemu/qemu/commit/880ae7de5958a765699386777de0f3841d635e1d
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_rtc.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  pseries: Move rtc_offset into RTC device's state structure

The initial creation of the PAPR RTC qdev class left a wart - the rtc's
offset was left in the sPAPREnvironment structure, accessed via a global.

This patch moves it into the RTC device's own state structure, were it
belongs.  This requires a small change to the migration stream format.  In
order to handle incoming streams from older versions, we also need to
retain the rtc_offset field in the sPAPREnvironment structure, so that it
can be loaded into via the vmsd, then pushed into the RTC device.

Since we're changing the migration format, this also takes the opportunity
to:

  * Change the rtc offset from a value in seconds to a value in
    nanoseconds, allowing nanosecond offsets between host and guest
    rtc time, if desired.

  * Remove both the already unused "next_irq" field and now unused
    "rtc_offset" field from the new version of the spapr migration
    stream

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 74e5ae284b1c8ac36a77e57ab9a49178173c666f
      
https://github.com/qemu/qemu/commit/74e5ae284b1c8ac36a77e57ab9a49178173c666f
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_rtc.c

  Log Message:
  -----------
  pseries: Export RTC time via QOM

On x86, the guest's RTC can be read with QMP, either from the RTC device's
"date" property or via the "rtc-time" property on the machine (which is an
alias to the former).  This is set up in the mc146818rtc driver, and
doesn't work on other targets.

This patch adds a similar "date" property to the pseries machine's RTAS RTC
and adds a compatible alias to the machine.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: fe656ebd4e4339972bae771a692109fd43ff5737
      
https://github.com/qemu/qemu/commit/fe656ebd4e4339972bae771a692109fd43ff5737
  Author: Markus Armbruster <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/e500.c

  Log Message:
  -----------
  PPC: Clean up misuse of qdev_init() in kvm-openpic creation

We call ppce500_init_mpic_kvm() to create a "kvm-openpic".  If it
fails, we call ppce500_init_mpic_qemu() to fall back to plain
"openpic".

ppce500_init_mpic_kvm() uses qdev_init().  qdev_init()'s error
handling has an unwanted side effect: it calls qerror_report_err(),
which prints to stderr.  Looks like an error, but isn't.

In QMP context, it would stash the error in the monitor instead,
making the QMP command fail.  Fortunately, it's only called from board
initialization, never in QMP context.

Clean up by cutting out the qdev_init() middle-man: set property
"realized" directly.

While there, improve the error message when we can't satisfy an
explicit user request for "kvm-openpic", and exit(1) instead of
abort().

Signed-off-by: Markus Armbruster <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 34f2af3d3edf9d57c27811d3780cbc0ece319625
      
https://github.com/qemu/qemu/commit/34f2af3d3edf9d57c27811d3780cbc0ece319625
  Author: Markus Armbruster <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Clean up misuse of qdev_init() in xics-kvm creation

We call try_create_xics() to create a "xics-kvm".  If it fails, we
call it again to fall back to plain "xics".

try_create_xics() uses qdev_init().  qdev_init()'s error handling has
an unwanted side effect: it calls qerror_report_err(), which prints to
stderr.  Looks like an error, but isn't.

In QMP context, it would stash the error in the monitor instead,
making the QMP command fail.  Fortunately, it's only called from board
initialization, never in QMP context.

Clean up by cutting out the qdev_init() middle-man: set property
"realized" directly.

While there, improve the error message when we can't satisfy an
explicit user request for "xics-kvm", and exit(1) instead of abort().
Simplify the abort when we can't create "xics".

Signed-off-by: Markus Armbruster <address@hidden>
[agraf: squash in fix for uninitialized variable from mdroth]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3c2784fc864d943ff70a2a5c9dea8e9a9b4d9e1d
      
https://github.com/qemu/qemu/commit/3c2784fc864d943ff70a2a5c9dea8e9a9b4d9e1d
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/display/vga-pci.c

  Log Message:
  -----------
  vga: Expose framebuffer byteorder as a QOM property

The VGA device model now supports having the framebuffer in either endian,
and can be switched between these by the guest via a register in the qext
region.

However, in some cases (e.g. LE OS on the pseries machine) we have
existing guest that don't know about the endian switch register, but other
parts of the qemu code have better information to set a default endianness
than the VGA code does of itself.

In order to allow them to set a correct default endianness in these cases,
without breaking abstraction walls, this patch exposes the VGA framebuffer
endianness via a writable QOM property.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Gerd Hoffmann <address@hidden>
[agraf: use instance_init for property exposure]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: eefaccc02bab659c8cb4c994b2f385c3f0a27551
      
https://github.com/qemu/qemu/commit/eefaccc02bab659c8cb4c994b2f385c3f0a27551
  Author: David Gibson <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_pci.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  pseries: Switch VGA endian on H_SET_MODE

When the guest switches the interrupt endian mode, which essentially
means a global machine endian switch, we want to change the VGA
framebuffer endian mode as well in order to be backward compatible
with existing guests who don't know about the new endian control
register.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 04d2acbb57900f1cba2eef86b21ab78d854683db
      
https://github.com/qemu/qemu/commit/04d2acbb57900f1cba2eef86b21ab78d854683db
  Author: Fabien Chouteau <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/intc/openpic.c

  Log Message:
  -----------
  Openpic: check that cpu id is within the number of cpus

Signed-off-by: Fabien Chouteau <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 21e5d28a4798f536525338f4f9137d83a9556491
      
https://github.com/qemu/qemu/commit/21e5d28a4798f536525338f4f9137d83a9556491
  Author: Tristan Gingold <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  display cpu id dump state

Signed-off-by: Fabien Chouteau <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 026359238b50f56a90961d9aa62ef303371eca8c
      
https://github.com/qemu/qemu/commit/026359238b50f56a90961d9aa62ef303371eca8c
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/misc/macio/macio.c

  Log Message:
  -----------
  macio.c: include parent PCIDevice state in VMStateDescription

This ensures that the macio PCI device is correctly configured when restoring
from a VM snapshot.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e5dffaa5b19b284718b40a4aba01abf0bcdabf7a
      
https://github.com/qemu/qemu/commit/e5dffaa5b19b284718b40a4aba01abf0bcdabf7a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/input/adb.c

  Log Message:
  -----------
  adb.c: include ADBDevice parent state in KBDState and MouseState

The parent ADBDevice contains the device id on the ADB bus. Make sure that
this state is included in both its subclasses since some clients (such as
OpenBIOS) reprogram each device id after enumeration.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6cb577dde5c2e19025f4f24fdff46c47ba8cd398
      
https://github.com/qemu/qemu/commit/6cb577dde5c2e19025f4f24fdff46c47ba8cd398
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/misc/macio/cuda.c

  Log Message:
  -----------
  cuda.c: include adb_poll_timer in VMStateDescription

Make sure that we include the adb_poll_timer when saving the VM state for
client OSs that use it, e.g. Darwin.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2828c4cd92b1c0590b959ec022888b1f6909949a
      
https://github.com/qemu/qemu/commit/2828c4cd92b1c0590b959ec022888b1f6909949a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M target-ppc/misc_helper.c
    M target-ppc/mmu_helper.c

  Log Message:
  -----------
  target-ppc: move sdr1 value change detection logic to helper_store_sdr1()

Otherwise when cpu_post_load calls ppc_store_sdr1() when restoring a VM
snapshot the value is deemed unchanged and so the internal env->htab*
variables aren't set correctly.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2360b6e84f78d41fa0f76555a947148b73645259
      
https://github.com/qemu/qemu/commit/2360b6e84f78d41fa0f76555a947148b73645259
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M target-ppc/machine.c

  Log Message:
  -----------
  target-ppc: force update of msr bits in cpu_post_load

Since env->msr has already been restored by the time cpu_post_load is called,
make sure that ppc_store_msr() is explicitly called with all msr bits except
MSR_TGPR marked as invalid.

This solves the issue where MSR flags aren't set correctly when restoring a VM
snapshot, in particular the internal env->excp_prefix value when MSR_EP has
been altered by a guest.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4efef9864082c8daa2a0fcff2d5bc0bfca221d1f
      
https://github.com/qemu/qemu/commit/4efef9864082c8daa2a0fcff2d5bc0bfca221d1f
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/intc/openpic.c

  Log Message:
  -----------
  openpic: fix segfault on -M mac99 savevm

A simple copy/paste error causes savevm on -M mac99 to segfault.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 032ab092904ce1615e3cedcb9ebc775bd3d7fac6
      
https://github.com/qemu/qemu/commit/032ab092904ce1615e3cedcb9ebc775bd3d7fac6
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/intc/openpic.c

  Log Message:
  -----------
  openpic: fix up loadvm under -M mac99

Issuing loadvm under -M mac99 would fail for two reasons: firstly an incorrect
version number for openpic would cause openpic_load() to abort, and secondly
a cut/paste error when restoring the IVPR and IDR registers caused subsequent
vmstate sections to become misaligned and abort early.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2ada66f944c0db9d037c7cf3ff1a4fd43283338d
      
https://github.com/qemu/qemu/commit/2ada66f944c0db9d037c7cf3ff1a4fd43283338d
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/intc/openpic.c

  Log Message:
  -----------
  openpic: switch IRQQueue queue from inline to bitmap

This is in preparation for using VMSTATE_BITMAP in a followup vmstate
migration patch.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e5f6e7327a95bf4c7e9354cd00e03d7ffaf25f8e
      
https://github.com/qemu/qemu/commit/e5f6e7327a95bf4c7e9354cd00e03d7ffaf25f8e
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/intc/openpic.c

  Log Message:
  -----------
  openpic: convert to vmstate

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Reviewed-by: Juan Quintela <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 28b07e737eb58f299b066c1c6b3740bb055a2cf9
      
https://github.com/qemu/qemu/commit/28b07e737eb58f299b066c1c6b3740bb055a2cf9
  Author: Markus Armbruster <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/char/spapr_vty.c
    M hw/net/spapr_llan.c
    M hw/nvram/spapr_nvram.c
    M hw/ppc/spapr_vio.c
    M hw/scsi/spapr_vscsi.c
    M include/hw/ppc/spapr_vio.h

  Log Message:
  -----------
  spapr_vio: Convert to realize()

Bonus fix: always set an error on failure.  Some failures were silent
before, except for the generic error set by device_realize().

Signed-off-by: Markus Armbruster <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 25e1727884493596bfeecb8af569442983400a34
      
https://github.com/qemu/qemu/commit/25e1727884493596bfeecb8af569442983400a34
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M default-configs/ppc64-softmmu.mak

  Log Message:
  -----------
  Revert "default-configs/ppc64: add all components of i82378 SuperIO chip used 
by prep"

This reverts commit 9c9984242ce46ccf8636f5c19e81d794e84aa0c7 as even when
it was applied, all supposedly new config options were already enabled.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 46ca0116657c225db0d7d3ee4fb0ed9fbf072257
      
https://github.com/qemu/qemu/commit/46ca0116657c225db0d7d3ee4fb0ed9fbf072257
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M default-configs/ppc64-softmmu.mak

  Log Message:
  -----------
  ppc64-softmmu: Remove duplicated OPENPIC from config

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6494ad9bf4f6e1561f078337d6d82018fd6e7516
      
https://github.com/qemu/qemu/commit/6494ad9bf4f6e1561f078337d6d82018fd6e7516
  Author: Alexander Graf <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M default-configs/ppcemb-softmmu.mak

  Log Message:
  -----------
  PPC: Remove duplicate OPENPIC defines in default-configs

The CONFIG_OPENPIC variable was declared multiple times. We only need it once.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3ba55e399f7637d2b4054bcc30228cd2d0883823
      
https://github.com/qemu/qemu/commit/3ba55e399f7637d2b4054bcc30228cd2d0883823
  Author: Cyril Bur <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  PPC: Introduce the Virtual Time Base (VTB) SPR register

This patch adds basic support for the VTB.

PowerISA:
The Virtual Time Base (VTB) is a 64-bit incrementing counter.
Virtual Time Base increments at the same rate as the Time Base until its value
becomes 0xFFFF_FFFF_FFFF_FFFF (2 64 - 1); at the next increment its value
becomes 0x0000_0000_0000_0000. There is no interrupt or other indication when
this occurs.

The operation of the Virtual Time Base has the following additional
properties.
1. Loading a GPR from the Virtual Time Base has no effect on the accuracy of
the Virtual Time Base.
2. Copying the contents of a GPR to the Virtual Time Base replaces the
contents of the Virtual Time Base with the contents of the GPR.

Signed-off-by: Cyril Bur <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: d7586dc426472b5ad0f5c01b5c7c551eeb5a6003
      
https://github.com/qemu/qemu/commit/d7586dc426472b5ad0f5c01b5c7c551eeb5a6003
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h

  Log Message:
  -----------
  target-ppc: Add versions to server CPU descriptions

5b79b1c "target-ppc: Create versionless CPU class per family if KVM" added
a dynamic CPU class registration with the name of the CPU family which
QEMU is running on. For example, this allowed specifying "-cpu POWER7"
on every version of POWER7 machine, not just the one which POWER7 was
an alias of. I.e. before 5b79b1c, "-cpu POWER7" would not work on real
POWER7 2.1 and would work on POWER7 2.3 only. The same story for POWER8.

However that patch broke POWER5+ support as POWER5+ CPU uses the same
name as the CPU class so dynamic registering of the POWER5+ class failed.

This redefines POWER5+ server CPUs by adding a version to them and adding
an alias for TCG case. KVM will use dynamically registered CPUs.

While we are here, do the same for 970 CPU.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ee954280da8d9ea7afd28b4c288da15fb8b4efca
      
https://github.com/qemu/qemu/commit/ee954280da8d9ea7afd28b4c288da15fb8b4efca
  Author: Gavin Shan <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  sPAPR: Implement EEH RTAS calls

The emulation for EEH RTAS requests from guest isn't covered
by QEMU yet and the patch implements them.

The patch defines constants used by EEH RTAS calls and adds
callbacks sPAPRPHBClass::{eeh_set_option, eeh_get_state, eeh_reset,
eeh_configure}, which are going to be used as follows:

  * RTAS calls are received in spapr_pci.c, sanity check is done
    there.
  * RTAS handlers handle what they can. If there is something it
    cannot handle and the corresponding sPAPRPHBClass callback is
    defined, it is called.
  * Those callbacks are only implemented for VFIO now. They do ioctl()
    to the IOMMU container fd to complete the calls. Error codes from
    that ioctl() are transferred back to the guest.

[aik: defined RTAS tokens for EEH RTAS calls]
Signed-off-by: Gavin Shan <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2aad88f4b05303531bc9aad6531258616d95af52
      
https://github.com/qemu/qemu/commit/2aad88f4b05303531bc9aad6531258616d95af52
  Author: Gavin Shan <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M hw/ppc/spapr_pci_vfio.c
    M hw/vfio/common.c

  Log Message:
  -----------
  sPAPR: Implement sPAPRPHBClass EEH callbacks

The patch implements sPAPRPHBClass EEH callbacks so that the EEH
RTAS requests can be routed to VFIO for further handling.

Signed-off-by: Gavin Shan <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a9ab06d1187f5967d315052da948afba6c3ba651
      
https://github.com/qemu/qemu/commit/a9ab06d1187f5967d315052da948afba6c3ba651
  Author: Stefan Weil <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M target-ppc/mmu-hash64.c

  Log Message:
  -----------
  target-ppc: Fix warnings from Sparse

Sparse report:

target-ppc/mmu-hash64.c:353:9: warning: returning void-valued expression
target-ppc/mmu-hash64.c:620:9: warning: returning void-valued expression

Signed-off-by: Stefan Weil <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 277263e1b320d759a760ba6c5ea75ec268f929e5
      
https://github.com/qemu/qemu/commit/277263e1b320d759a760ba6c5ea75ec268f929e5
  Author: Peter Maydell <address@hidden>
  Date:   2015-03-09 (Mon, 09 Mar 2015)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M default-configs/ppc64-softmmu.mak
    M default-configs/ppcemb-softmmu.mak
    M hw/char/spapr_vty.c
    M hw/display/vga-pci.c
    M hw/input/adb.c
    M hw/intc/openpic.c
    M hw/misc/macio/cuda.c
    M hw/misc/macio/macio.c
    M hw/net/spapr_llan.c
    M hw/nvram/spapr_nvram.c
    M hw/ppc/Makefile.objs
    M hw/ppc/e500.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_pci_vfio.c
    M hw/ppc/spapr_rtas.c
    A hw/ppc/spapr_rtc.c
    M hw/ppc/spapr_vio.c
    M hw/scsi/spapr_vscsi.c
    M hw/timer/mc146818rtc.c
    M hw/vfio/common.c
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_vio.h
    M include/migration/vmstate.h
    M include/qom/object.h
    M qom/object.c
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/cpu.h
    M target-ppc/machine.c
    M target-ppc/misc_helper.c
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu-hash64.h
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' 
into staging

Patch queue for ppc - 2015-03-09

This is my current patch queue for 2.3. Highlights include:

  * pseries: 2.3 machine
  * pseries: Export RTC via QOM
  * pseries: EEH support
  * mac: save/restore support
  * fix POWER5 hosts
  * random bug fixes

# gpg: Signature made Mon Mar  9 14:00:53 2015 GMT using RSA key ID 03FEDC60
# gpg: Good signature from "Alexander Graf <address@hidden>"
# gpg:                 aka "Alexander Graf <address@hidden>"

* remotes/agraf/tags/signed-ppc-for-upstream: (38 commits)
  target-ppc: Fix warnings from Sparse
  sPAPR: Implement sPAPRPHBClass EEH callbacks
  sPAPR: Implement EEH RTAS calls
  target-ppc: Add versions to server CPU descriptions
  PPC: Introduce the Virtual Time Base (VTB) SPR register
  PPC: Remove duplicate OPENPIC defines in default-configs
  ppc64-softmmu: Remove duplicated OPENPIC from config
  Revert "default-configs/ppc64: add all components of i82378 SuperIO chip used 
by prep"
  spapr_vio: Convert to realize()
  openpic: convert to vmstate
  openpic: switch IRQQueue queue from inline to bitmap
  openpic: fix up loadvm under -M mac99
  openpic: fix segfault on -M mac99 savevm
  target-ppc: force update of msr bits in cpu_post_load
  target-ppc: move sdr1 value change detection logic to helper_store_sdr1()
  cuda.c: include adb_poll_timer in VMStateDescription
  adb.c: include ADBDevice parent state in KBDState and MouseState
  macio.c: include parent PCIDevice state in VMStateDescription
  display cpu id dump state
  Openpic: check that cpu id is within the number of cpus
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/0048fa6c807f...277263e1b320