[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] e13951: target-ppc: Fix target_disas
|
From: |
GitHub |
|
Subject: |
[Qemu-commits] [qemu/qemu] e13951: target-ppc: Fix target_disas |
|
Date: |
Mon, 16 Jun 2014 11:00:08 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: e13951f8962a069d3172c1bd22f44a4cf5d2c1c9
https://github.com/qemu/qemu/commit/e13951f8962a069d3172c1bd22f44a4cf5d2c1c9
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M disas.c
Log Message:
-----------
target-ppc: Fix target_disas
Inspect only bit 16 for the Little Endian test. Correct comment preceding
the target_disas() function. Correct grammar in comment for flags processing.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 1c38f84373dd0a360883a343f6f50a5c0c856dec
https://github.com/qemu/qemu/commit/1c38f84373dd0a360883a343f6f50a5c0c856dec
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M disas.c
M monitor.c
Log Message:
-----------
monitor: QEMU Monitor Instruction Disassembly Incorrect for PowerPC LE Mode
The monitor support for disassembling instructions does not honor the MSR[LE]
bit for PowerPC processors.
This change enhances the monitor_disas() routine by supporting a flag bit
for Little Endian mode. Bit 16 is used since that bit was used in the
analagous guest disassembly routine target_disas().
Also, to be consistent with target_disas(), the disassembler bfd_mach field
can be passed in the flags argument.
Reported-by: Anton Blanchard <address@hidden>
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: d5843485894e30133ee0f70deda0f1118e539be4
https://github.com/qemu/qemu/commit/d5843485894e30133ee0f70deda0f1118e539be4
Author: Fabien Chouteau <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/net/fsl_etsec/rings.c
Log Message:
-----------
Fix typo in eTSEC Ethernet controller
IRQ are lowered when ievent bit is cleared, so irq_pulse makes no sense
here...
Signed-off-by: Fabien Chouteau <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 4e2ca12785dc94f4b0abd532cacc44386ee14506
https://github.com/qemu/qemu/commit/4e2ca12785dc94f4b0abd532cacc44386ee14506
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/nvram/spapr_nvram.c
Log Message:
-----------
spapr_nvram: Correct max nvram size
Currently it is UINT16_MAX*16 = 65536*16 = 1048560 which is not
a round number and therefore a bit confusing.
This defines MAX_NVRAM_SIZE precisely as 1MB.
Suggested-by: Thomas Huth <address@hidden>
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: c46e98310608b806382b036d973e2ada8e7275c3
https://github.com/qemu/qemu/commit/c46e98310608b806382b036d973e2ada8e7275c3
Author: Thomas Falcon <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/gdbstub.c
Log Message:
-----------
target-ppc: extract register length calculation in gdbstub
This patch extracts the method to determine a register's size
into a separate function.
Reviewed-by: Andreas Färber <address@hidden>
Signed-off-by: Thomas Falcon <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 8a286ce4502356ce0b97a2424a2cb7dfb31567f2
https://github.com/qemu/qemu/commit/8a286ce4502356ce0b97a2424a2cb7dfb31567f2
Author: Thomas Falcon <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/gdbstub.c
Log Message:
-----------
target-ppc: gdbstub allow byte swapping for reading/writing registers
This patch allows registers to be properly read from and written to
when using the gdbstub to debug a ppc guest running in little
endian mode.
Reviewed-by: Andreas Färber <address@hidden>
Signed-off-by: Thomas Falcon <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 5b79b1cadd3e565b6d1a5ba59764bd47af58b271
https://github.com/qemu/qemu/commit/5b79b1cadd3e565b6d1a5ba59764bd47af58b271
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
target-ppc: Create versionless CPU class per family if KVM
At the moment generic version-less CPUs are supported via hardcoded aliases.
For example, POWER7 is an alias for POWER7_v2.1. So when QEMU is started
with -cpu POWER7, the POWER7_v2.1 class instance is created.
This approach works for TCG and KVMs other than HV KVM. HV KVM cannot emulate
PVR value so the guest always sees the real PVR. HV KVM will not allow setting
PVR other that the host PVR because of that (the kernel patch for it is on
its way). So in most cases it is impossible to run QEMU with -cpu POWER7
unless the host PVR is exactly the same as the one from the alias (which
is now POWER7_v2.3). It was decided that under HV KVM QEMU should use
-cpu host.
Using "host" CPU type creates a problem for management tools such as libvirt
because they want to know in advance if the destination guest can possibly
run on the destination. Since the "host" type is really not a type and will
always work with any KVM, there is no way for libvirt to know if the migration
will success.
This registers additional CPU class derived from the host CPU family.
The name for it is taken from @desc field of the CPU family class.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: fdf8a960e2a00c1f670d89de3368069924c88243
https://github.com/qemu/qemu/commit/fdf8a960e2a00c1f670d89de3368069924c88243
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Move alias lookup after class lookup
This moves aliases lookup after CPU class lookup. This is to let new generic
CPU to be found first if it is present and only if it is not (TCG case), use
aliases.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 70d246c335d7fef745c3068f109926a8cee08220
https://github.com/qemu/qemu/commit/70d246c335d7fef745c3068f109926a8cee08220
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu-models.c
M target-ppc/cpu-models.h
Log Message:
-----------
target-ppc: Remove redundant POWER7 declarations
At the moment there are 3 versions of POWER7 CPUs defined. However
we do not emulate these CPUs diffent and it does not make much
sense to keep them all.
This removes POWER7_v2.0 and POWER7_v2.1 and leaves just one versioned
CPU per family which is POWER7_v2.3 with POWER7 alias.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: fabe9ee1133b606390f6ca463ddb490051cba760
https://github.com/qemu/qemu/commit/fabe9ee1133b606390f6ca463ddb490051cba760
Author: Greg Kurz <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr-pci: remove io ports workaround
In the past, IO space could not be mapped into the memory address space
so we introduced a workaround for that. Nowadays it does not look
necessary so we can remove the workaround and make sPAPR PCI
configuration simplier.
Signed-off-by: Greg Kurz <address@hidden>
Acked-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: b26696b519f853c9844e5154858e583600ee3cdc
https://github.com/qemu/qemu/commit/b26696b519f853c9844e5154858e583600ee3cdc
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr_pci: Fix number of returned vectors in ibm, change-msi
Current guest kernels try allocating as many vectors as the quota is.
For example, in the case of virtio-net (which has just 3 vectors)
the guest requests 4 vectors (that is the quota in the test) and
the existing ibm,change-msi handler returns 4. But before it returns,
it calls msix_set_message() in a loop and corrupts memory behind
the end of msix_table.
This limits the number of vectors returned by ibm,change-msi to
the maximum supported by the actual device.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Cc: address@hidden
[agraf: squash in bugfix from aik]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9df5a46632dca802f382ae61d2d3d0fdbfb185a5
https://github.com/qemu/qemu/commit/9df5a46632dca802f382ae61d2d3d0fdbfb185a5
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Eliminate Magic Number MSR Masks
Use MSR mnemonics from cpu.h instead of magic numbers for the
CPUPPCState.msr_mask
initialization.
There is one bit in the 401x2 (and subsequent) model that I could not find any
documentation for. It is open coded at little endian bit position 20:
pcc->msr_mask = (1ull << 20) |
(1ull << MSR_KEY) |
(1ull << MSR_POW) |
(1ull << MSR_CE) |
...
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 569be9f0551f5941335afa525b2b83d4dfb4210c
https://github.com/qemu/qemu/commit/569be9f0551f5941335afa525b2b83d4dfb4210c
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/machine.c
Log Message:
-----------
target-ppc: Remove PVR check from migration
Currently migration fails if CPU version (PVR register) is different
even a bit. This check is performed at the very end of migration when
device states are sent. This is too late for management software and
we need to provide a way for the user to make sure that migration
will succeed if QEMU is started with appropritate command line parameters.
This removes the PVR check.
This resets PVR to the default value as the existing VMSTATE record
for SPR array sends all 1024 registers unconditionally and overwrites
the destination PVR.
If the user wants some guarantees for migration to succeed, then
a CPU name or "host" CPU with a "compat" option (on its way to upsteam)
should be used and KVM or TCG is expected to fail on unsupported values
at the moment of QEMU start.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9d1c128341df7a303571f172d986291b4f3ed9ee
https://github.com/qemu/qemu/commit/9d1c128341df7a303571f172d986291b4f3ed9ee
Author: BALATON Zoltan <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M include/hw/ppc/ppc.h
Log Message:
-----------
mac99: Added FW_CFG_PPC_BUSFREQ to match CLOCKFREQ and TBFREQ already there
While there, also moved the hard coded value for CLOCKFREQ to a #define.
Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 72ac97cdfc0592b567cb62582300c0d707701bb1
https://github.com/qemu/qemu/commit/72ac97cdfc0592b567cb62582300c0d707701bb1
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
A include/libdecnumber/dconfig.h
A include/libdecnumber/decContext.h
A include/libdecnumber/decDPD.h
A include/libdecnumber/decNumber.h
A include/libdecnumber/decNumberLocal.h
A include/libdecnumber/dpd/decimal128.h
A include/libdecnumber/dpd/decimal128Local.h
A include/libdecnumber/dpd/decimal32.h
A include/libdecnumber/dpd/decimal64.h
A libdecnumber/decContext.c
A libdecnumber/decNumber.c
A libdecnumber/dpd/decimal128.c
A libdecnumber/dpd/decimal128Local.h
A libdecnumber/dpd/decimal32.c
A libdecnumber/dpd/decimal64.c
Log Message:
-----------
libdecnumber: Introduce libdecnumber Code
Add files from the libdecnumber decimal floating point library to QEMU. The
libdecnumber
library was originally part of GCC and contains code that is useful in
emulating the PowerPC
decimal floating point (DFP) instructions. This particular copy of the source
comes from
GCC 4.3 and is licensed at GPLv2+.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: f5d7f1464692433fc0ff2c3418ef9ad3e14d3a3d
https://github.com/qemu/qemu/commit/f5d7f1464692433fc0ff2c3418ef9ad3e14d3a3d
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/libdecnumber/decContext.h
M include/libdecnumber/decDPD.h
M include/libdecnumber/decNumber.h
M include/libdecnumber/decNumberLocal.h
M include/libdecnumber/dpd/decimal128.h
M include/libdecnumber/dpd/decimal32.h
M include/libdecnumber/dpd/decimal64.h
Log Message:
-----------
libdecnumber: Eliminate #include *Symbols.h
The various *Symbols.h files were not copied from the original GCC libdecnumber
library; they are not necessary for use in QEMU. Remove all instances of
#include "*Symbols.h"
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 0f2d3732202818fb85c09d1c204a08c4d79b70bc
https://github.com/qemu/qemu/commit/0f2d3732202818fb85c09d1c204a08c4d79b70bc
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/libdecnumber/decNumber.h
M include/libdecnumber/decNumberLocal.h
M include/libdecnumber/dpd/decimal128.h
M include/libdecnumber/dpd/decimal32.h
M include/libdecnumber/dpd/decimal64.h
M libdecnumber/decContext.c
M libdecnumber/decNumber.c
M libdecnumber/dpd/decimal128.c
M libdecnumber/dpd/decimal32.c
M libdecnumber/dpd/decimal64.c
Log Message:
-----------
libdecnumber: Prepare libdecnumber for QEMU include structure
Consistent with other libraries in QEMU, the libdecnumber header files were
placed in include/libdecnumber, separate from the C code. This is different
from the original libdecnumber source, where they were co-located.
Change the libdecnumber source code so that it reflects this split.
Specifically,
modify directives of the form:
#include "xxx.h"
to look like:
#include "libdecnumber/xxx.h"
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 7275585b8c0dda0720255c45489045b0c31092cc
https://github.com/qemu/qemu/commit/7275585b8c0dda0720255c45489045b0c31092cc
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/libdecnumber/dconfig.h
Log Message:
-----------
libdecnumber: Modify dconfig.h to Integrate with QEMU
Modify the dconfig.h header file so that libdecnumber code integrates QEMU
configuration. Specifically:
- the WORDS_BIGENDIAN preprocessor macro is used in libdecnumber code to
determines endianness. It is derived from the existing QEMU macro
HOST_WORDS_BIGENDIAN which is defined in config-host.h.
- the DECPUN macro determines the number of decimal digits (aka declets) per
unit (byte). This is 3 for PowerPC DFP.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9b7a14b0640110cbb1017c4b701b96dddc659d37
https://github.com/qemu/qemu/commit/9b7a14b0640110cbb1017c4b701b96dddc659d37
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/libdecnumber/decContext.h
Log Message:
-----------
libdecnumber: Change gstdint.h to stdint.h
Replace the inclusion of gstdint.h with the standard stdint.h
header file.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 426d9a1a59e07ebcde3ec55c8b7997e44ce34d2d
https://github.com/qemu/qemu/commit/426d9a1a59e07ebcde3ec55c8b7997e44ce34d2d
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M libdecnumber/dpd/decimal128.c
M libdecnumber/dpd/decimal32.c
M libdecnumber/dpd/decimal64.c
Log Message:
-----------
libdecnumber: Eliminate redundant declarations
Eliminate redundant declarations of symbols DPD2BIN and BIN2DPD in
various .c source files. These symbols are already declared in decDPD.h and
thus will trigger 'redundant redeclaration of ?XXX?' warnings, which, of
course, may fail QEMU compilation.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 4922fd7d526e2740c18cee69cd371a32dcb2049a
https://github.com/qemu/qemu/commit/4922fd7d526e2740c18cee69cd371a32dcb2049a
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M libdecnumber/decNumber.c
Log Message:
-----------
libdecnumber: Eliminate Unused Variable in decSetSubnormal
Eliminate an unused variable in the decSetSubnormal routine. The
variable dnexp is declared and eventually set but never used, and
thus may trigger an unused-but-set-variable warning.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e58f8d1ff9f1f71bb1162ccd2f05c258ca8efdbe
https://github.com/qemu/qemu/commit/e58f8d1ff9f1f71bb1162ccd2f05c258ca8efdbe
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M Makefile.target
M default-configs/ppc-linux-user.mak
M default-configs/ppc-softmmu.mak
M default-configs/ppc64-linux-user.mak
M default-configs/ppc64-softmmu.mak
M default-configs/ppc64abi32-linux-user.mak
M default-configs/ppcemb-softmmu.mak
Log Message:
-----------
target-ppc: Enable Building of libdecnumber
Enable compilation of the newly added libdecnumber library code.
Object file targets are added to Makefile.target using a newly
introduced flag CONFIG_LIBDECNUMBER. The flag is added
to the PowerPC targets (ppc[64]-linux-user, ppc[64]-softmmu).
Signed-off-by: Tom Musta <address@hidden>
[agraf: add ppcemb and ppc64abi32 config]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 8e706db21ecfba75da3f9f843f1fa36276085742
https://github.com/qemu/qemu/commit/8e706db21ecfba75da3f9f843f1fa36276085742
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/libdecnumber/decNumber.h
M libdecnumber/decNumber.c
Log Message:
-----------
libdecnumber: Introduce decNumberFrom[U]Int64
Introduce two conversion functions to the libdecnumber library.
These conversions transform 64 bit integers to the internal decNumber
representation. Both a signed and unsigned version is added.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 79af3572250352c5eeacdd813b57ad5ba748654c
https://github.com/qemu/qemu/commit/79af3572250352c5eeacdd813b57ad5ba748654c
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/libdecnumber/decNumber.h
M include/libdecnumber/decNumberLocal.h
M libdecnumber/decContext.c
M libdecnumber/decNumber.c
Log Message:
-----------
libdecnumber: Introduce decNumberIntegralToInt64
Introduce a new conversion function to the libdecnumber library.
This function converts a decNumber to a signed 64-bit integer.
In order to support 64-bit integers (which may have up to 19
decimal digits), the existing "powers of 10" array is expanded
from 10 to 19 entries.
Signed-off-by: Tom Musta <address@hidden>
[agraf: fix 32bit host compile]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 0a322e7e7cc25267fb4f900d4bc193a134cd72fe
https://github.com/qemu/qemu/commit/0a322e7e7cc25267fb4f900d4bc193a134cd72fe
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M libdecnumber/decNumber.c
Log Message:
-----------
libdecnumber: Fix decNumberSetBCD
Fix a simple bug in the decNumberSetBCD() function. This function
encodes a decNumber with "n" BCD digits. The original code erroneously
computed the number of declets from the dn argument, which is the output
decNumber value, and hence may contain garbage. Instead, the input "n"
value is used.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: a4f27cc82c5ebf7691cc9de26c368dac6d302526
https://github.com/qemu/qemu/commit/a4f27cc82c5ebf7691cc9de26c368dac6d302526
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/helper.h
Log Message:
-----------
target-ppc: Define FPR Pointer Type for Helpers
Define a floating pointer register pointer type in the PowerPC
helper header. The type will be used to pass FPR register operands
to Decimal Floating Point (DFP) helpers. A pointer is used because
the quad word forms of PowerPC DFP instructions operate on adjacent
pairs of floating point registers and thus can be thought of as
arrays of length 2.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: f0b01f02a44d29bc41af2a87a22732c9449e5dd8
https://github.com/qemu/qemu/commit/f0b01f02a44d29bc41af2a87a22732c9449e5dd8
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce Generator Macros for DFP Arithmetic Forms
Add general support for generators of PowerPC Decimal Floating Point helpers.
Some utilities are annotated with GCC attribute unused in order to preserve
build bisection. These annotations will be removed in later patches.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 275e35c6c1e2aa82eacb0ee13eb80fabeee66bbf
https://github.com/qemu/qemu/commit/275e35c6c1e2aa82eacb0ee13eb80fabeee66bbf
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce Decoder Macros for DFP
Add decoder macros for the various Decimal Floating Point
instruction forms. Illegal instruction masks are used to not only
guard against reserved instruction field use, but also to catch
illegal quad word forms that use odd-numbered floating point registers.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 7b0c0d66e54868087b6db6a302aba030c0c5f2c3
https://github.com/qemu/qemu/commit/7b0c0d66e54868087b6db6a302aba030c0c5f2c3
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/Makefile.objs
A target-ppc/dfp_helper.c
Log Message:
-----------
target-ppc: Introduce DFP Helper Utilities
Add a new file (dfp_helper.c) to the PowerPC implementation for Decimal Floating
Point (DFP) emulation. This first version of the file declares a structure that
will be used by DFP helpers. It also implements utilities that will initialize
such a structure for either a long (64 bit) DFP instruction or an extended (128
bit, aka "quad") instruction.
Some utility functions are annotated with the unused attribute in order to
preserve
build bisection.
Signed-off-by: Tom Musta <address@hidden>
[agraf: Add never reached assert on dfp_prepare_rounding_mode()]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 27722744e9fc81e437a5e55db8ec31ec99b31714
https://github.com/qemu/qemu/commit/27722744e9fc81e437a5e55db8ec31ec99b31714
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
Log Message:
-----------
target-ppc: Introduce DFP Post Processor Utilities
Add post-processing utilities to the PowerPC Decimal Floating Point
(DFP) helper code. Post-processors are small routines that execute
after a preliminary DFP result is computed. They are used, among other
things, to compute status bits.
This change defines a function type for post processors as well as a
generic routine to run a list (array) of post-processors.
Actual post-processor implementations will be added as needed by specific
DFP helpers in subsequent changes.
Some routines are annotated with the GCC unused attribute in order to
preserve build bisection. The annotation will be removed in subsequent
patches.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: a9d7ba03b0fa8c7b6d660c6aafa736d16921728f
https://github.com/qemu/qemu/commit/a9d7ba03b0fa8c7b6d660c6aafa736d16921728f
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Add
Add emulation of the PowerPC Decimal Floating Point Add instructions dadd[q][.]
Various GCC unused annotations are removed since it is now safe to remove them.
Signed-off-by: Tom Musta <address@hidden>
[agraf: move brace in function definition]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 2128f8a57e1f1db97b8ba03eae4d8e5d94bf1ea5
https://github.com/qemu/qemu/commit/2128f8a57e1f1db97b8ba03eae4d8e5d94bf1ea5
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Subtract
Add emulation of the PowerPC Decimal Floating Point Subtract instructions
dsub[q][.]
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 8de6a1cc672d94e6ca793a1a7fcccf48b65b2e89
https://github.com/qemu/qemu/commit/8de6a1cc672d94e6ca793a1a7fcccf48b65b2e89
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Multiply
Add emulation of the PowerPC Decimal Floating Point Multiply instructions
dmul[q][.]
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9024ff40ba79f77b027fb3cbfe584e0005128193
https://github.com/qemu/qemu/commit/9024ff40ba79f77b027fb3cbfe584e0005128193
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Divide
Add emulation of the PowerPC Decimal Floating Point Divide instructions
ddiv[q][.]
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 5833505be64a27f8ae7a503d3f39b9d586b0d5f6
https://github.com/qemu/qemu/commit/5833505be64a27f8ae7a503d3f39b9d586b0d5f6
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Compares
Add emulation of the PowerPC Decimal Floating Point Compare instructions
dcmpu[q] and dcmpo[q].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e601c1eead579b9a849dc4bfc2da2038cef361fd
https://github.com/qemu/qemu/commit/e601c1eead579b9a849dc4bfc2da2038cef361fd
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Test Data Class
Add emulation of the PowerPC Decimal Floating Point Test Data Class
instructions dtstdc[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 1bf9c0e1339858505841117727cf10455171641f
https://github.com/qemu/qemu/commit/1bf9c0e1339858505841117727cf10455171641f
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Test Data Group
Add emulation of the PowerPC Decimal Floating Point Test Data
Group instructions dtstdg[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: f3d2b0bce098456539ea16eb92af6197b68dc8d8
https://github.com/qemu/qemu/commit/f3d2b0bce098456539ea16eb92af6197b68dc8d8
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Test Exponent
Add emulation of the PowerPC Decimal Floating Point Test Exponent
instructions dtstex[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: f6022a7684042b441b953ea27795afa897bcd35c
https://github.com/qemu/qemu/commit/f6022a7684042b441b953ea27795afa897bcd35c
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Test Significance
Add emulation of the PowerPC Decimal Floating Point Test Significance
instructions dtstsf[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 5826ebe27a0cc865eb0458105836353fb044649e
https://github.com/qemu/qemu/commit/5826ebe27a0cc865eb0458105836353fb044649e
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Quantize
Add emulation of the PowerPC Decimal Floating Point Quantize instructions
dquai[q][.] and dqua[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 512918aa79da893aa85d80319a54b891d7d8c10f
https://github.com/qemu/qemu/commit/512918aa79da893aa85d80319a54b891d7d8c10f
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Reround
Add emulation of the PowerPC Decimal Floating Point Reround instructions
drrnd[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 97c0d93041857cf64ceddbf59f37cf396af7fe21
https://github.com/qemu/qemu/commit/97c0d93041857cf64ceddbf59f37cf396af7fe21
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Round to Integer
Add emulation of the PowerPC Decimal Floating Point (DFP) Round
to FP Integer With Inexact (drintx[q][.]) and DFP Round to FP
Integer Without Inexact (drintn[q][.]) instructions.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 290d9ee53790f67528b0d48865c93cc045c1eece
https://github.com/qemu/qemu/commit/290d9ee53790f67528b0d48865c93cc045c1eece
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Convert to Long/Extended
Add emulation of the PowerPC Convert to DFP Long (dctdp[.]) and
Convert to DFP Extended (dctqpq[.]) instructions.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: ca603eb4d7015dc9e88b4d325e837950117ad124
https://github.com/qemu/qemu/commit/ca603eb4d7015dc9e88b4d325e837950117ad124
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce Round to DFP Short/Long
Add emulation of the PowerPC Round to DFP Short (drsp[.]) and Round to
DFP Long (drdpq[.]) instructions.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: f12141935512fd8e5de1ecbb6494be86ec8880a5
https://github.com/qemu/qemu/commit/f12141935512fd8e5de1ecbb6494be86ec8880a5
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Convert to Fixed
Add emulation of the PowerPC Decimal Floating Point Convert to
Fixed instructions dctfix[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: bea0dd7912ee91c0219f143db7bb8350fade98c4
https://github.com/qemu/qemu/commit/bea0dd7912ee91c0219f143db7bb8350fade98c4
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Convert to Fixed
Add emulation of the PowerPC Decimal Floating Point Convert to Fixed
instructions dctfix[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 7796676fddc9f6b035c6a9fd872258b53c7d8644
https://github.com/qemu/qemu/commit/7796676fddc9f6b035c6a9fd872258b53c7d8644
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Decode DPD to BCD
Add emulation of the Power PC Decimal Floating Point Decode
Densely Packed Decimal to Binary Coded Decimal instructions
ddedpd[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 013c3ac070497b2577ae3be444928963e7ac5ab5
https://github.com/qemu/qemu/commit/013c3ac070497b2577ae3be444928963e7ac5ab5
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Encode BCD to DPD
Add emulation of the PowerPC Decimal Floating Point Encode Binary
Coded Decimal to Densely Packed Decimal instructions denbcd[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e8a484603146f7e2523749ad06e6ea43b26cf411
https://github.com/qemu/qemu/commit/e8a484603146f7e2523749ad06e6ea43b26cf411
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Extract Biased Exponent
Add emulation of the PowerPC Decimal Floating Point Extract
Biased Exponent instructions dxex[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 297666eba0f6d73b5969763aec2b3f8ac4123b9a
https://github.com/qemu/qemu/commit/297666eba0f6d73b5969763aec2b3f8ac4123b9a
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Insert Biased Exponent
Add emulation of the PowerPC Decimal Floating Point Insert Biased
Exponent instructions diex[q][.].
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 804e654a56549c2960f9c3857bec4f4d934b437e
https://github.com/qemu/qemu/commit/804e654a56549c2960f9c3857bec4f4d934b437e
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/dfp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Introduce DFP Shift Significand
Add emulation of the PowerPC Decimal Floating Point Shift Significand
Left Immediate (dscli[q][.]) and DFP Shift Significant Right Immediate
(dscri[q][.]) instructions.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 28668b5f31b05f6413826e110ff909522759f7d9
https://github.com/qemu/qemu/commit/28668b5f31b05f6413826e110ff909522759f7d9
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr_pci: fix MSI limit
At the moment XICS does not support interrupts reuse so sPAPR PHB
implements this. sPAPRPHBState holds array of 32 spapr_pci_msi to
describe PCI config address, first MSI and number of MSIs. Once
allocated for a device, QEMU tries reusing this config until the number
of MSIs changes.
Existing SPAPR guests call ibm,change-msi in a loop until the handler
returns the requested number of vectors.
Recently introduced check for the maximum number of MSI/MSIX vectors
supported by a device only works for a device which is new for PHB's
MSI cache. If it is already there, the check is not performed which
leads to new IRQ block allocation. This happens during PCI hotplug
even when the user hot plug the same device which he just hot unplugged.
This moves the check earlier.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 40c84b54dd47f3ad2a170c036a97aa1b777c645d
https://github.com/qemu/qemu/commit/40c84b54dd47f3ad2a170c036a97aa1b777c645d
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/qemu/aes.h
M util/aes.c
Log Message:
-----------
util: Add S-Box and InvS-Box Arrays to Common AES Utils
This patch adds tables for the S-Box and InvS-Box transformations commonly used
by various
Advanced Encription Standard (AES) instruction models.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 1c1a6d20e0bceef5b5ce68930bf255021c326cce
https://github.com/qemu/qemu/commit/1c1a6d20e0bceef5b5ce68930bf255021c326cce
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/qemu/aes.h
M util/aes.c
Log Message:
-----------
util: Add AES ShiftRows and InvShiftRows Tables
This patch adds tables that implement the Advanced Encryption Standard (AES)
ShiftRows
and InvShiftRows transformations. These are commonly used in instruction
models.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: bfd8f5b754318a933e052374c3c17d314bd9927c
https://github.com/qemu/qemu/commit/bfd8f5b754318a933e052374c3c17d314bd9927c
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/qemu/aes.h
M util/aes.c
Log Message:
-----------
util: Add InvMixColumns
This patch adds the table implementation of the Advanced Encryption Standard
(AES)
InvMixColumns transformation.
The patch is intentionally asymmetrical -- the MixColumns table is not added
because
there is no known use for it at this time.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 04af534d55f23a024cb21864b073bd6d1da7dcf6
https://github.com/qemu/qemu/commit/04af534d55f23a024cb21864b073bd6d1da7dcf6
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-i386/ops_sse.h
Log Message:
-----------
target-i386: Use Common ShiftRows and InvShiftRows Tables
This patch eliminates the (now) redundant copy of the Advanced Encryption
Standard (AES)
ShiftRows and InvShiftRows tables; the code is updated to use the common tables
declared in
include/qemu/aes.h.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 59dcd29a6c4f89e946fd320539afbfc1859e826e
https://github.com/qemu/qemu/commit/59dcd29a6c4f89e946fd320539afbfc1859e826e
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-arm/crypto_helper.c
Log Message:
-----------
target-arm: Use Common Tables in AES Instructions
This patch refactors the ARM cryptographic instructions to use the
(newly) added common tables from include/qemu/aes.h.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: c15424531f2406cf5ad9f02d35204fac98601696
https://github.com/qemu/qemu/commit/c15424531f2406cf5ad9f02d35204fac98601696
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/int_helper.c
Log Message:
-----------
target-ppc: Refactor AES Instructions
This patch refactors the PowerPC Advanced Encryption Standard (AES) instructions
to use the common AES tables (include/qemu/aes.h).
Specifically:
- vsbox is recoded to use the AES_sbox table.
- vcipher, vcipherlast and vncipherlast are all recoded to use the optimized
AES_t[ed][0-4] tables.
- vncipher is recoded to use a combination of InvS-Box, InvShiftRows and
InvMixColumns tables. It was not possible to use AES_Td[0-4] due to a
slight difference in how PowerPC implements vncipher.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 08215d8fd8ca15425401adc9e01361cbc6882402
https://github.com/qemu/qemu/commit/08215d8fd8ca15425401adc9e01361cbc6882402
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
KVM: PPC: Don't secretly add 1T segment feature to CPU
When we select a CPU type that does not support 1TB segments, we should
not expose 1TB just because KVM supports 1TB segments. User configuration
always wins over feature availability.
Signed-off-by: Alexander Graf <address@hidden>
Commit: d575a6ce0efb96966240a53bf611ad6bf5a14ebd
https://github.com/qemu/qemu/commit/d575a6ce0efb96966240a53bf611ad6bf5a14ebd
Author: Bharat Bhushan <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/pci-host/ppce500.c
M hw/ppc/e500.c
Log Message:
-----------
PPC: e500: some pci related cleanup
- Use PCI_NUM_PINS rather than hardcoding
- use "pin" wherever possible
Signed-off-by: Bharat Bhushan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 3016dca06cba0ef9511f1c81c7e73bfc805fb254
https://github.com/qemu/qemu/commit/3016dca06cba0ef9511f1c81c7e73bfc805fb254
Author: Bharat Bhushan <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/pci-host/ppce500.c
M hw/ppc/e500.c
Log Message:
-----------
PPC: e500: implement PCI INTx routing
This patch adds pci pin to irq_num routing callback.
This callback is called from pci_device_route_intx_to_irq to
find which pci device maps to which irq.
This fix is required for pci-device passthrough using vfio.
Also without this patch we gets below prints
"
PCI: Bug - unimplemented PCI INTx routing (e500-pcihost)
qemu-system-ppc64: PCI: Bug - unimplemented PCI INTx routing (e500-pcihost) "
and Legacy interrupt does not work with pci device passthrough.
Signed-off-by: Bharat Bhushan <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
[agraf: remove double semicolon]
Signed-off-by: Alexander Graf <address@hidden>
Commit: c80d1df5083846396ab5120731a76a9d62900fda
https://github.com/qemu/qemu/commit/c80d1df5083846396ab5120731a76a9d62900fda
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
PPC: Fix TCG chunks that don't free their temps
We want to make sure that every instruction cleans up after itself and
clears every temporary it allocated.
While checking whether this is already the case, I came across a few
cases where it isn't. This patch fixes every translation I found that
doesn't free their allocated temporaries.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 3de31797825e94fd67ee7c2e877127acc3d2edbd
https://github.com/qemu/qemu/commit/3de31797825e94fd67ee7c2e877127acc3d2edbd
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
PPC: Fail on leaking temporaries
When QEMU gets compiled with --enable-debug-tcg we can check for temporary
leakage. Implement the necessary target code for this and fail emulation
when we hit a leakage.
This hopefully ensures that we don't get new leaks.
Signed-off-by: Alexander Graf <address@hidden>
Commit: f1d9ec8bf73d893cf225030a55d1a006e7ebccee
https://github.com/qemu/qemu/commit/f1d9ec8bf73d893cf225030a55d1a006e7ebccee
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu-models.c
Log Message:
-----------
PPC: Make all e500 CPUs SVR aware
Our pre-e500mc e500 CPU types didn't get instanciated with SVR information,
even though those systems do support the SVR register.
Spawn them with the SVR tag so that they don't get confused when someone tries
to read SPR_SVR.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 45eb56110bcefef473f866772a7b537be1b3fe35
https://github.com/qemu/qemu/commit/45eb56110bcefef473f866772a7b537be1b3fe35
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
Log Message:
-----------
PPC: Add definitions for GIVORs
We're missing SPR definitions for GIVORs. Add them to the list of SPRs.
Signed-off-by: Alexander Graf <address@hidden>
Commit: deb05c4c4c2b7bfeccddb8494164cc858a8652ec
https://github.com/qemu/qemu/commit/deb05c4c4c2b7bfeccddb8494164cc858a8652ec
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
PPC: Fix SPR access control of L1CFG0
The L1CFG0 register on e200 and e500 is "User RO" according to the
specifications. So let's make it user readable and world unwritable.
Signed-off-by: Alexander Graf <address@hidden>
Commit: d2ea2bf740c515de41f45e4d6f36683db3458881
https://github.com/qemu/qemu/commit/d2ea2bf740c515de41f45e4d6f36683db3458881
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
PPC: Add L1CFG1 SPR emulation
In addition to the L1 data cache configuration register L1CFG0 there is
also another one for the L1 instruction cache called L1CFG1.
Emulate that one with the same values as the data one.
Signed-off-by: Alexander Graf <address@hidden>
Commit: ea71258da4b8141d8a808d94518a0964c0f92810
https://github.com/qemu/qemu/commit/ea71258da4b8141d8a808d94518a0964c0f92810
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
PPC: Properly emulate L1CSR0 and L1CSR1
There are 2 L1 cache control registers - one for data (L1CSR0) and
one for instructions (L1CSR1).
Emulate both of them well enough to give the guest the illusion that
it could actually do anything about its caches.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 4d09d5291dac27b48fd597c72de6fddaa4d74571
https://github.com/qemu/qemu/commit/4d09d5291dac27b48fd597c72de6fddaa4d74571
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
PPC: Add dcbtls emulation
The dcbtls instruction is able to lock data inside the L1 cache.
Unfortunately we don't emulate any caches, so we have to tell the guest
that its locking attempt failed.
However, by implementing the instruction we at least don't give the
guest a program exception which it definitely does not expect.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 903585dec63ee83bd8149006e31f92ea789b38e3
https://github.com/qemu/qemu/commit/903585dec63ee83bd8149006e31f92ea789b38e3
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
PPC: e500: Expose kernel load address in dt
We want to move to a model where firmware loads our kernel. To achieve
this we need to be able to tell firmware where the kernel lies.
Let's copy the mechanism we already use for -M pseries and expose the
kernel load address and size through the device tree.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 4e73c781923fd5b7608db65156cfa72c4b31ba1d
https://github.com/qemu/qemu/commit/4e73c781923fd5b7608db65156cfa72c4b31ba1d
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M .gitmodules
M configure
M pc-bios/README
A pc-bios/u-boot.e500
M roms/Makefile
A roms/u-boot
Log Message:
-----------
PPC: Add u-boot firmware for e500
This adds a special build of u-boot tailored for the e500 platforms we
emulate. It is based on the current version of upstream u-boot which
contains all the code necessary to drive our QEMU provided machines.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 3812c71ffaa2cf733c3087792b859fef30b7545f
https://github.com/qemu/qemu/commit/3812c71ffaa2cf733c3087792b859fef30b7545f
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
PPC: e500: Move to u-boot as firmware
Almost all platforms QEMU emulates have some sort of firmware they can load
to expose a guest environment that closely resembles the way it would look
like on real hardware.
This patch introduces such a firmware on our e500 platforms. U-boot is the
default firmware for most of these systems and as such our preferred choice.
For backwards compatibility reasons (and speed and simplicity) we skip u-boot
when you use -kernel and don't pass in -bios. For all other combinations like
-kernel and -bios or no -kernel you get u-boot as firmware.
This allows you to modify the boot environment, execute a networked boot through
the e1000 emulation and execute u-boot payloads.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 98a8b52442d3e35c640f21d79cf9551a2e408073
https://github.com/qemu/qemu/commit/98a8b52442d3e35c640f21d79cf9551a2e408073
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
M target-ppc/cpu-qom.h
M target-ppc/kvm.c
M trace-events
Log Message:
-----------
spapr: Add support for time base offset migration
This allows guests to have a different timebase origin from the host.
This is needed for migration, where a guest can migrate from one host
to another and the two hosts might have a different timebase origin.
However, the timebase seen by the guest must not go backwards, and
should go forwards only by a small amount corresponding to the time
taken for the migration.
This is only supported for recent POWER hardware which has the TBU40
(timebase upper 40 bits) register. That includes POWER6, 7, 8 but not
970.
This adds kvm_access_one_reg() to access a special register which is not
in env->spr. This requires kvm_set_one_reg/kvm_get_one_reg patch.
The feature must be present in the host kernel.
This bumps vmstate_spapr::version_id and enables new vmstate_ppc_timebase
only for it. Since the vmstate_spapr::minimum_version_id remains
unchanged, migration from older QEMU is supported but without
vmstate_ppc_timebase.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 10582ff832798813ba3a17f13f3ab46250388b47
https://github.com/qemu/qemu/commit/10582ff832798813ba3a17f13f3ab46250388b47
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Add ibm, chip-id property in device tree
This adds a "ibm,chip-id" property for CPU nodes which should be the same
for all cores in the same CPU socket. The recent guest kernels use this
information to associate threads with sockets.
Refer to the kernel commit 256f2d4b463d3030ebc8d2b54f427543814a2bdc
for more details.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 85720d36676ef0b765a69f1e312b4c9d4ff6fa16
https://github.com/qemu/qemu/commit/85720d36676ef0b765a69f1e312b4c9d4ff6fa16
Author: Mark Cave-Ayland <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ide/macio.c
Log Message:
-----------
macio: handle non-block ATAPI DMA transfers
Currently the macio DMA routines assume that all DMA requests are for read/write
block transfers. This is not always the case for ATAPI, for example when
requesting a TOC where the response is generated directly in the IDE buffer.
Detect these non-block ATAPI DMA transfers (where no lba is specified in the
command) and copy the results directly into RAM as indicated by the DBDMA
descriptor. This fixes CDROM access under MorphOS.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: acb0ef5801fc0caafdcfd34ae62e48d276866a1b
https://github.com/qemu/qemu/commit/acb0ef5801fc0caafdcfd34ae62e48d276866a1b
Author: Bharata B Rao <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M dump.c
A include/sysemu/dump-arch.h
M include/sysemu/dump.h
M stubs/dump.c
Log Message:
-----------
dump: Make DumpState and endian conversion routines available for
arch-specific dump code
Make DumpState and endian conversion routines available for arch-specific dump
code by moving into dump.h. DumpState will be needed by arch-specific dump
code to access target endian information from DumpState->ArchDumpInfo. Also
break the dependency of dump.h from stubs/dump.c by creating a separate
dump-arch.h.
This patch doesn't change any functionality.
Signed-off-by: Bharata B Rao <address@hidden>
[ rebased on top of current master branch,
renamed endian helpers to cpu_to_dump{16,32,64},
pass a DumpState * argument to endian helpers,
Greg Kurz <address@hidden> ]
Signed-off-by: Greg Kurz <address@hidden>
[agraf: fix to apply]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 0c967de9c00321f893a57617a4e3dfcda05266f5
https://github.com/qemu/qemu/commit/0c967de9c00321f893a57617a4e3dfcda05266f5
Author: Bharata B Rao <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/arch_dump.c
Log Message:
-----------
target-ppc: Support dump for little endian ppc64
Fix ppc64 arch specific dump code to support all combinations of little/big
endian hosts/guests. FWIW the current code is broken for altivec registers
when guest and host have a different endianness: these 128-bit registers
are written to guest memory as a two 64-bit entities and we should also swap
them.
Unit testing was done with the following program provided by Tom Musta:
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
int main(int argc, char** argv)
{
__uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) |
0x08090a0b0c0d0e0full;
register void * vptr asm ("r11");
vptr = &v;
for(;;)
asm volatile ("lvx 30,0,11" );
}
When sending SIGABRT to this program and examining the core file, we get:
- ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
- ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
We expect to find the very same layout in the QEMU dump since they are
real core files. This is what we get:
- ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
- ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
- x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
- x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
We introduce a NoteFuncArg type to avoid adding extra arguments to all note
functions.
Signed-off-by: Bharata B Rao <address@hidden>
[ rebased on top of current master branch,
introduced NoteFuncArg,
use new cpu_to_dump{16,32,64} endian helpers,
fix altivec support,
Greg Kurz <address@hidden> ]
Reviewed-by: Alexander Graf <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 382d2db62bcb34dff7febc270783d5ff662ced7a
https://github.com/qemu/qemu/commit/382d2db62bcb34dff7febc270783d5ff662ced7a
Author: Greg Kurz <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu-qom.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Introduce callback for interrupt endianness
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
special purpose register to decide the endianness to use when
entering interrupt handlers. When running a Linux guest, this
provides a hint on the endianness used by the kernel. And when
it comes to dumping a guest, the information is needed to write
ELF headers using the kernel endianness.
Suggested-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
[agraf: change subject line]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 1e6ed54ef84c5c131216bcef44930970eee8f687
https://github.com/qemu/qemu/commit/1e6ed54ef84c5c131216bcef44930970eee8f687
Author: Bharata B Rao <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/arch_dump.c
Log Message:
-----------
target-ppc: Set the correct endianness in ELF dump header
Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 8ebe65f3611b265ed093bdc3300624aa11990503
https://github.com/qemu/qemu/commit/8ebe65f3611b265ed093bdc3300624aa11990503
Author: Paul Janzen <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/intc/openpic.c
Log Message:
-----------
openpic: Move definition of openpic_reset
This patch moves the definition of openpic_reset after the various
register read/write functions. No functional change. It is in
preparation for using the register read/write functions in
openpic_reset.
Signed-off-by: Paul Janzen <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: ffd5e9fe02763a0e943dbb76fa78100ef5513e48
https://github.com/qemu/qemu/commit/ffd5e9fe02763a0e943dbb76fa78100ef5513e48
Author: Paul Janzen <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/intc/openpic.c
Log Message:
-----------
openpic: Reset IRQ source private members
The openpic emulation code maintains an allowable-CPU's bitmap
("destmask") for each IRQ source which is calculated from the IDR
register value whenever the guest OS writes to it. However, if the
guest OS relies on the system to set the IDR register to a default
value at reset, and does not write IDR, then destmask does not get
updated, and interrupts do not get propagated to the guest.
Additionally, if an IRQ source is marked as critical, the source's
internal "output" and "nomask" fields are not correctly reset when the
PIC is reset.
Fix both these issues by calling write_IRQreg_idr from within
openpic_reset, instead of simply setting the IDR register to the
specified idr_reset value.
Signed-off-by: Paul Janzen <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: af354f19a9b6a655eac1c49b66d3be021e7ed3d9
https://github.com/qemu/qemu/commit/af354f19a9b6a655eac1c49b66d3be021e7ed3d9
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/intc/openpic_kvm.c
Log Message:
-----------
PPC: openpic_kvm: Implement reset
When we trigger a system reset, the in-kernel openpic controller should also
get reset. This happens through a write to the GCR.RESET register which is
the same mechanism a guest would use to manually reset the device.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 8dfa3a5e85eca94a93b1495136f49c5776fd5ada
https://github.com/qemu/qemu/commit/8dfa3a5e85eca94a93b1495136f49c5776fd5ada
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu-models.h
M target-ppc/cpu-qom.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add "compat" CPU option
PowerISA defines a compatibility mode for server POWERPC CPUs which
is supported by the PCR special register which is hypervisor privileged.
To support this mode for guests, SPAPR defines a set of virtual PVRs,
one per PowerISA spec version. When a hypervisor needs a guest to work in
a compatibility mode, it puts a virtual PVR value into @cpu-version
property of a CPU node.
This introduces a "compat" CPU option which defines maximal compatibility
mode enabled. The supported modes are power6/power7/power8.
This does not change the existing behaviour, new property will be used
by next patches.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 833d46685d2c59078d484ca22708d9b46283fbd4
https://github.com/qemu/qemu/commit/833d46685d2c59078d484ca22708d9b46283fbd4
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Move SMT-related properties out of skeleton fdt
The upcoming support of the "ibm,client-architecture-support"
reconfiguration call will be able to change dynamically the number
of threads per core (SMT mode). From the device tree prospective
this does not change the number of CPU nodes (as it is one node per
a CPU core) but affects content and size of the ibm,ppc-interrupt-server#s
and ibm,ppc-interrupt-gserver#s properties.
This moves ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s
out of the device tree skeleton.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 6d9412ea8132d6fa23bb0d57167ea585c728c3f1
https://github.com/qemu/qemu/commit/6d9412ea8132d6fa23bb0d57167ea585c728c3f1
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
M target-ppc/cpu-qom.h
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Implement "compat" CPU option
This adds basic support for the "compat" CPU option. By specifying
the compat property, the user can manually switch guest CPU mode from
"raw" to "architected".
This defines feature disable bits which are not used yet as, for example,
PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter -
transactional memory (TM) will be disabled because 2.06 does not define
it at all. The same is true for VSX and 2.05 mode. So just setting a mode
must be ok.
This does not change the existing behavior as the actual compatibility
mode support is coming in next patches.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
[agraf: fix compilation on 32bit hosts]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 1a68b71419406235bbde205463f2bd7e4ffe5b26
https://github.com/qemu/qemu/commit/1a68b71419406235bbde205463f2bd7e4ffe5b26
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu-qom.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Define Processor Compatibility Masks
This introduces PCR mask for supported compatibility modes.
This will be used later by the ibm,client-architecture-support call.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 2a6593cb6a2d72c8c29e14f89413089fa5d38501
https://github.com/qemu/qemu/commit/2a6593cb6a2d72c8c29e14f89413089fa5d38501
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
M trace-events
Log Message:
-----------
spapr: Add ibm, client-architecture-support call
The PAPR+ specification defines a ibm,client-architecture-support (CAS)
RTAS call which purpose is to provide a negotiation mechanism for
the guest and the hypervisor to work out the best compatibility parameters.
During the negotiation process, the guest provides an array of various
options and capabilities which it supports, the hypervisor adjusts
the device tree and (optionally) reboots the guest.
At the moment the Linux guest calls CAS method at early boot so SLOF
gets called. SLOF allocates a memory buffer for the device tree changes
and calls a custom KVMPPC_H_CAS hypercall. QEMU parses the options,
composes a diff for the device tree, copies it to the buffer provided
by SLOF and returns to SLOF. SLOF updates the device tree and returns
control to the guest kernel. Only then the Linux guest parses the device
tree so it is possible to avoid unnecessary reboot in most cases.
The device tree diff is a header with an update format version
(defined as 1 in this patch) followed by a device tree with the properties
which require update.
If QEMU detects that it has to reboot the guest, it silently does so
as the guest expects reboot to happen because this is usual pHyp firmware
behavior.
This defines custom KVMPPC_H_CAS hypercall. The current SLOF already
has support for it.
This implements stub which returns very basic tree (root node,
no properties) to the guest.
As the return buffer does not contain any change, no change in behavior is
expected.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 82677ed2f5d700d2344689bea30d75887f9a8cf4
https://github.com/qemu/qemu/commit/82677ed2f5d700d2344689bea30d75887f9a8cf4
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Rework spapr_fixup_cpu_dt()
In PPC code we usually use the "cs" name for a CPUState* variables
and "cpu" for PowerPCCPU. So let's change spapr_fixup_cpu_dt() to
use same rules as spapr_create_fdt_skel() does.
This adds missing nodes creation if they do not already exist in
the current device tree, this is going to be used from
the client-architecture-support handler.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 2a48d99335c572b0d3da59c1387ad131ea6ee590
https://github.com/qemu/qemu/commit/2a48d99335c572b0d3da59c1387ad131ea6ee590
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
spapr: Limit threads per core according to current compatibility mode
This puts a limit to the number of threads per core based on the current
compatibility mode. Although PowerISA specs do not specify the maximum
threads per core number, the linux guest still expects that
PowerISA2.05-compatible CPU supports only 2 threads per core as this
is what POWER6 (2.05 compliant CPU) implements, the same is for
POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads).
This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of
threads which affects ibm,ppc-interrupt-server#s and
ibm,ppc-interrupt-gserver#s properties.
The number of CPU nodesremains unchanged.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 3794d5482d74dc0031cee6d5be2c61c88ca723bd
https://github.com/qemu/qemu/commit/3794d5482d74dc0031cee6d5be2c61c88ca723bd
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M trace-events
Log Message:
-----------
spapr: Implement processor compatibility in ibm, client-architecture-support
Modern Linux kernels support last POWERPC CPUs so when a kernel boots,
in most cases it can find a matching cpu_spec in the kernel's cpu_specs
list. However if the kernel is quite old, it may be missing a definition
of the actual CPU. To provide an ability for old kernels to work on modern
hardware, a Processor Compatibility Mode has been introduced
by the PowerISA specification.
>From the hardware prospective, it is supported by the Processor
Compatibility Register (PCR) which is defined in PowerISA. The register
enables one of the compatibility modes (2.05/2.06/2.07).
Since PCR is a hypervisor privileged register and cannot be
directly accessed from the guest, the mode selection is done via
ibm,client-architecture-support (CAS) RTAS call using which the guest
specifies what "raw" and "architected" CPU versions it supports.
QEMU works out the best match, changes a "cpu-version" property of
every CPU and notifies the guest about the change by setting these
properties in the buffer passed as a response on a custom H_CAS hypercall.
This implements ibm,client-architecture-support parameters parsing
(now only for PVRs) and cooks the device tree diff with new values for
"cpu-version", "ibm,ppc-interrupt-server#s" and
"ibm,ppc-interrupt-server#s" properties.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 6db5bb0f547b0a0889e8c2ee330f789916813e94
https://github.com/qemu/qemu/commit/6db5bb0f547b0a0889e8c2ee330f789916813e94
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
M target-ppc/translate_init.c
Log Message:
-----------
KVM: PPC: Enable compatibility mode
The host kernel implements a KVM_REG_PPC_ARCH_COMPAT register which
this uses to enable a compatibility mode if any chosen.
This sets the KVM_REG_PPC_ARCH_COMPAT register in KVM. ppc_set_compat()
signals the caller if the mode cannot be enabled by the host kernel.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
[agraf: fix TCG compat setting]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 00d4f525ec8d9394c4e86e36f01ac68d30128dd6
https://github.com/qemu/qemu/commit/00d4f525ec8d9394c4e86e36f01ac68d30128dd6
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_iommu.c
Log Message:
-----------
spapr_iommu: Replace @instance_id with LIOBN for migration
SPAPR IOMMU is a bus-less device and therefore its only ID in
migration stream is an instance id which is not reliable ID
as it depends on the command line parameters order. Since
libvirt may change the order, we need something better than that.
This removes VMSD descriptor from the class definitiion and
registers it with @liobn as an intance ID to let the destination
side find the right device to receive migration data.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 6ab39b1bd3474aab57e10cc90377b9a3b94a72d4
https://github.com/qemu/qemu/commit/6ab39b1bd3474aab57e10cc90377b9a3b94a72d4
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Fix popcntb Opcode Bug
The popcntb instruction is erroneously encoded with opcode extension
(opc1,opc2) = (0x03,0x03).
Bits 21-30 of popcntb are 122 = 0b00011-0b11010 and therefore this should be
encoded
as (opc1,opc2) = (0x1A, 0x03).
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 3e300fa6ad4ee19b16339c25773dec8df0bfb982
https://github.com/qemu/qemu/commit/3e300fa6ad4ee19b16339c25773dec8df0bfb982
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ide/macio.c
M hw/misc/macio/mac_dbdma.c
M include/hw/ppc/mac_dbdma.h
Log Message:
-----------
macio ide: Do remainder access asynchronously
The macio IDE controller has some pretty nasty magic in its implementation to
allow for unaligned sector accesses. We used to handle these accesses
synchronously inside the IO callback handler.
However, the block infrastructure changed below our feet and now it's impossible
to call a synchronous block read/write from the aio callback handler of a
previous block access.
Work around that limitation by making the unaligned handling bits also go
through our asynchronous handler.
This fixes booting Mac OS X for me.
Reported-by: John Arbuckle <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9397a7c8318d727cea2ac62dbb14493a0e3e5f4b
https://github.com/qemu/qemu/commit/9397a7c8318d727cea2ac62dbb14493a0e3e5f4b
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/misc/macio/macio.c
Log Message:
-----------
macio: Fix timer endianness
The timer registers on our KeyLargo macio emulation are read as byte reversed
from the big endian guest, so we better expose them endian reversed as well.
This fixes initial hickups of booting Mac OS X with -M mac99 for me.
Signed-off-by: Alexander Graf <address@hidden>
Tested-by: Mark Cave-Ayland <address@hidden>
Commit: a1d59c0ffadf17d546f53f4bda06e8adcf616ede
https://github.com/qemu/qemu/commit/a1d59c0ffadf17d546f53f4bda06e8adcf616ede
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Enable dynamic change of the supported hypercalls list
At the moment the "ibm,hypertas-functions" list is fixed. However some
calls should be listed there if they are supported by QEMU or the host
kernel.
This enables hyperrtas_prop to grow on stack by adding
a SPAPR_HYPERRTAS_ADD macro. "qemu,hypertas-functions" is converted as well.
The first user of this is going to be a "multi-tce" property.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: da95324ebe462b14a3507af02eb4a689c8a1619f
https://github.com/qemu/qemu/commit/da95324ebe462b14a3507af02eb4a689c8a1619f
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_iommu.c
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
M trace-events
Log Message:
-----------
spapr_iommu: Enable multiple TCE requests
Currently only single TCE entry per request is supported (H_PUT_TCE).
However PAPR+ specification allows multiple entry requests such as
H_PUT_TCE_INDIRECT and H_STUFF_TCE. Having less transitions to the host
kernel via ioctls, support of these calls can accelerate IOMMU operations.
This implements H_STUFF_TCE and H_PUT_TCE_INDIRECT.
This advertises "multi-tce" capability to the guest if the host kernel
supports it (KVM_CAP_SPAPR_MULTITCE) or guest is running in TCG mode.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: da6ccee4184482b45a2cb562c7373639792fc58d
https://github.com/qemu/qemu/commit/da6ccee4184482b45a2cb562c7373639792fc58d
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
Log Message:
-----------
spapr_pci: Introduce a finish_realize() callback
The spapr-pci PHB initializes IOMMU for emulated devices only.
The upcoming VFIO support will do it different. However both emulated
and VFIO PHB types share most of the initialization code.
For the type specific things a new finish_realize() callback is
introduced.
This introduces sPAPRPHBClass derived from PCIHostBridgeClass and
adds the callback pointer.
This implements finish_realize() for emulated devices.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
[agraf: Fix compilation]
Signed-off-by: Alexander Graf <address@hidden>
Commit: cca7fad5765251fece44cd230156a101867522dd
https://github.com/qemu/qemu/commit/cca7fad5765251fece44cd230156a101867522dd
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
Log Message:
-----------
spapr_pci: spapr_iommu: Make DMA window a subregion
Currently the default DMA window is represented by a single MemoryRegion.
However there can be more than just one window so we need
a "root" memory region to be separated from the actual DMA window(s).
This introduces a "root" IOMMU memory region and adds a subregion for
the default DMA 32bit window. Following patches will add other
subregion(s).
This initializes a default DMA window subregion size to the guest RAM
size as this window can be switched into "bypass" mode which implements
direct DMA mapping.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e28c16f61feefa197e04e83662f32bfc1d607723
https://github.com/qemu/qemu/commit/e28c16f61feefa197e04e83662f32bfc1d607723
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
Log Message:
-----------
spapr_pci: Allow multiple TCE tables per PHB
At the moment sPAPRPHBState contains a @tcet pointer to the only
TCE table. However sPAPR spec allows having more than one DMA window.
Since the TCE object is already a child of SPAPR PHB object, there is
no need to keep an additional pointer to it in sPAPRPHBState so remove it.
This changes the way sPAPRPHBState::reset performs reset of sPAPRTCETable
objects.
This changes the default DMA window properties calculation.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e4c35b78bce645aaa299d3b7b62494c880c6c74d
https://github.com/qemu/qemu/commit/e4c35b78bce645aaa299d3b7b62494c880c6c74d
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_iommu.c
Log Message:
-----------
spapr_iommu: Convert old qdev_init_nofail() to object_property_set_bool
qdev_init_nofail() was replaced by object_property_set_bool("realized")
all over the QEMU so do we.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 523e7b8ab818ec3fab14cfd7a20d51cb3aa33a9d
https://github.com/qemu/qemu/commit/523e7b8ab818ec3fab14cfd7a20d51cb3aa33a9d
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M include/hw/pci-host/spapr.h
M include/hw/ppc/spapr.h
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
Log Message:
-----------
spapr_iommu: Get rid of window_size in sPAPRTCETable
This removes window_size as it is basically a copy of nb_table
shifted by SPAPR_TCE_PAGE_SHIFT. As new dynamic DMA windows are
going to support windows as big as the entire RAM and this number
will be bigger that 32 capacity, we will have to do something
about @window_size anyway and removal seems to be the right way to go.
This removes dma_window_start/dma_window_size from sPAPRPHBState as
they are no longer used.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 650f33adbd53b0bacdd5d3392ea5b11a8a0fba42
https://github.com/qemu/qemu/commit/650f33adbd53b0bacdd5d3392ea5b11a8a0fba42
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr_iommu: Introduce page_shift in sPAPRTCETable
At the moment only 4K pages are supported by sPAPRTCETable. Since sPAPR
spec allows other page sizes and we are going to implement them, we need
page size to be configrable.
This adds @page_shift into sPAPRTCETable and replaces SPAPR_TCE_PAGE_SHIFT
with it where it is possible.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 1b8eceee280d3fab11812271f4956f7b69287ef0
https://github.com/qemu/qemu/commit/1b8eceee280d3fab11812271f4956f7b69287ef0
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr_iommu: Introduce bus_offset in sPAPRTCETable
This adds @bus_offset into sPAPRTCETable to tell where TCE table starts
from. It is set to 0 for emulated devices. Dynamic DMA windows will use
other offset.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: a721d390b302a383a99224e08d12caad2e97d7ab
https://github.com/qemu/qemu/commit/a721d390b302a383a99224e08d12caad2e97d7ab
Author: Alex Zuepke <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/helper.h
M target-ppc/mmu_helper.c
M target-ppc/translate_init.c
Log Message:
-----------
PPC: e500: Fix MMUCSR0 emulation
A "mtspr SPRMMUCSR0, reg" always flushed TLB0,
because it passed the SPR number 0x3f4 to the flush routine.
But we want to flush either TLB0 or TBL1 depending on the GPR value.
Signed-off-by: Alex Zuepke <address@hidden>
[agraf: change subject line, fix TCGv size mismatch]
Signed-off-by: Alexander Graf <address@hidden>
Commit: d90b94cd78af672cdfd52dc3789ab249534c2f40
https://github.com/qemu/qemu/commit/d90b94cd78af672cdfd52dc3789ab249534c2f40
Author: Doug Kwan <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M include/elf.h
M linux-user/elfload.c
M linux-user/ppc/syscall.h
Log Message:
-----------
target-ppc: Support little-endian PPC64 in user mode.
Look at ELF header to determine ABI version on PPC64. This is required
for executing the first instruction correctly. Also print correct machine
name in uname() system call.
Signed-off-by: Doug Kwan <address@hidden>
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e22c357b3ec01c1141969ae81397d60d52e8c87b
https://github.com/qemu/qemu/commit/e22c357b3ec01c1141969ae81397d60d52e8c87b
Author: Doug Kwan <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M linux-user/main.c
M target-ppc/mem_helper.c
M target-ppc/translate.c
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Allow little-endian user mode.
This allows running PPC64 little-endian in user mode if target is configured
that way. In PPC64 LE user mode we set MSR.LE during initialization.
Signed-off-by: Doug Kwan <address@hidden>
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9c35126c56de54d0505ac7676ca4699af1d205bf
https://github.com/qemu/qemu/commit/9c35126c56de54d0505ac7676ca4699af1d205bf
Author: Doug Kwan <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M configure
A default-configs/ppc64le-linux-user.mak
Log Message:
-----------
target-ppc: Add a new user mode target for little-endian PPC64.
Signed-off-by: Doug Kwan <address@hidden>
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 5b274ed74d21929c5ec399b32f47ad46105b3721
https://github.com/qemu/qemu/commit/5b274ed74d21929c5ec399b32f47ad46105b3721
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Support VSX in PPC User Mode
Some modern tool chains use VSX instructions. Therefore attempt to enable the
VSX MSR
bit by default, just like similar bits (FP, VEC, SPE, etc.).
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: f46e9a0b9911fcfbc13f85f3a8808067990a0f5c
https://github.com/qemu/qemu/commit/f46e9a0b9911fcfbc13f85f3a8808067990a0f5c
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
target-ppc: Confirm That .bss Pages Are Valid
The existing code does a check to ensure that a .bss region is properly
mmap'd. When additional mmap is required, the (guest) pages are also
validated. However, this code has a bug: when host page size is larger
than target page size, it is possible for the .bss pages to already be
(host) mapped but the guest .bss pages may not be valid.
The check to mmap additional space is separated from the flagging of the
target (guest) pages, thus ensuring that both aspects are done properly.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 4b1daa72d3b68b050bb9013edd0888972a0e22dd
https://github.com/qemu/qemu/commit/4b1daa72d3b68b050bb9013edd0888972a0e22dd
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M linux-user/main.c
Log Message:
-----------
target-ppc: Store Quadword Conditional Drops Size Bit
The size and register information are encoded into the reserve_info field
of CPU state in the store conditional translation code. Specifically, the
size is shifted left by 5 bits (see target-ppc/translate.c
gen_conditional_store).
The user-mode store conditional code erroneously extracts the size by ANDing
with a 4 bit mask; this breaks if size >= 16.
Eliminate the mask to make the extraction of size mirror its encoding.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: f2e2bc9ca06a1c2c6b300c19d4b938c7273a2f76
https://github.com/qemu/qemu/commit/f2e2bc9ca06a1c2c6b300c19d4b938c7273a2f76
Author: Peter Maydell <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/pci-host/ppce500.c
Log Message:
-----------
hw/pci-host/ppce500: Fix typo in vmstate definition
Fix a typo in the ppce500_pci vmstate definition which meant that
we were migrating the struct pci_inbound using the vmstate for
pci_outbound. Fortunately the two structures have exactly the same
format at the moment (four uint32_ts) so this was harmless, and
we can correcting the typo without a migration compatibility
break because the vmstate name doesn't go out on the wire.
Signed-off-by: Peter Maydell <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: deb6ed13ebfcd6c73548225347c5f63225bb471f
https://github.com/qemu/qemu/commit/deb6ed13ebfcd6c73548225347c5f63225bb471f
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/mmu_helper.c
Log Message:
-----------
PPC: e500: Fix TLB lookup for 32bit CPUs
When we run 32bit guest CPUs (or 32bit guest code on 64bit CPUs) on
qemu-system-ppc64 the TLB lookup will use the full effective address
as pointer.
However, only the first 32bits are valid when MSR.CM = 0. Check for
that condition.
This makes QEMU boot an e500v2 guest with more than 1G of RAM for me.
Signed-off-by: Alexander Graf <address@hidden>
Commit: ada82b537e6fa947666a7cda1530529769a9324c
https://github.com/qemu/qemu/commit/ada82b537e6fa947666a7cda1530529769a9324c
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
PPC: SPE: Fix high-bits bitmask
The SPE emulation code wants to access the highest 32bits of a 64bit register
and uses the andi TCG instruction for that. Unfortunately it masked with the
wrong mask. Fix the mask to actually cover the upper 32 bits.
This fixes simple multiplication tests with SPE guests for me.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 2872e1929b771fdbc935a882f804f2dc0addc0f9
https://github.com/qemu/qemu/commit/2872e1929b771fdbc935a882f804f2dc0addc0f9
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M scripts/update-linux-headers.sh
Log Message:
-----------
linux-headers: include psci.h
The kvm headers now have a dependency on psci.h, sync it into our linux
header copy as well.
Signed-off-by: Alexander Graf <address@hidden>
Commit: b061808d39fa11ecc6c07cec7bef6676669c1f3e
https://github.com/qemu/qemu/commit/b061808d39fa11ecc6c07cec7bef6676669c1f3e
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M linux-headers/asm-arm/kvm.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-mips/kvm.h
M linux-headers/asm-powerpc/kvm.h
M linux-headers/asm-powerpc/kvm_para.h
M linux-headers/linux/kvm.h
A linux-headers/linux/psci.h
Log Message:
-----------
linux-headers: update linux headers to kvm/next
This updates the kvm headers to commit 820b3fcd in kvm/next.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 87a91de61a34a7f3222203556df8a67f187360cd
https://github.com/qemu/qemu/commit/87a91de61a34a7f3222203556df8a67f187360cd
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
Log Message:
-----------
KVM: PPC: Expose fixup hcall capability
New kvm versions expose a PPC_FIXUP_HCALL capability. Make it visible to
machine code so we can take decisions based on it.
Signed-off-by: Alexander Graf <address@hidden>
Commit: f7d69146549d717ef6cb5a68a3a4452391416f22
https://github.com/qemu/qemu/commit/f7d69146549d717ef6cb5a68a3a4452391416f22
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
PPC: spapr: Expose /hypervisor node in device tree
PR KVM supports an ePAPR compliant hypercall interface in parallel to the
normal sPAPR one. Expose the ePAPR /hypervisor node and properties to the
guest so it can use it.
This enables magic page sharing on PR KVM with -M pseries.
However we had a few nasty bugs in the magic page implementation on vcpus
newer than 970 (p7, p8) that KVM now has workarounds for. It indicates that
it does have these workarounds through the PPC_FIXUP_HCALL capability.
To not expose broken guest kernels to issues on host kernels that don't
have the fixups in place, we don't expose working hypercall instructions
when the fixups are not available so that the guest can never active the
magic page.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 13b6a455655068e6f86576c43ef070995dccaa40
https://github.com/qemu/qemu/commit/13b6a455655068e6f86576c43ef070995dccaa40
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate.c
Log Message:
-----------
PPC: e500: Merge 32 and 64 bit SPE emulation
Today we have a lot of conditional code in the SPE emulation depending on
whether we have 64bit GPRs or not.
Unfortunately the assumption that we can just recycle the 64bit GPR
implementation is wrong. Normal SPE implementations maintain the upper 32 bits
on all non-SPE instructions which then only modify the low 32 bits. However
all instructions we model that adhere to the normal SF based switching don't
care whether they operate on 32 or 64 bit registers and just always use the full
64 bits.
So let's remove that dubious SPE optimization and revert everything to the same
code path the 32bit target code was taking. That way we get rid of differences
between the two implementations, but will get a slight performance hit when
emulating SPE instructions.
This fixes SPE emulation with qemu-system-ppc64 for me.
Signed-off-by: Alexander Graf <address@hidden>
Commit: a9e8f4e7df385a6c704527d9c5b562f42566d491
https://github.com/qemu/qemu/commit/a9e8f4e7df385a6c704527d9c5b562f42566d491
Author: Tom Musta <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Fix Temporary Variable Leak in bctar
Fix a temporary variable leak detected in the bctar instruction:
Opcode 13 10 11 (4d910460) leaked temporaries
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: cb8b8bf840141e2874823b1ee8c0efa98f269708
https://github.com/qemu/qemu/commit/cb8b8bf840141e2874823b1ee8c0efa98f269708
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs
As defined in Linux kernel, PMC*, SIAR, MMCR0/1 have different numbers
for 32 and 64 bit POWERPC. We are going to support 64bit versions too so
let's rename 32bit ones to avoid confusion.
This is a mechanical patch so it does not fix obvious mistake with these
registers in POWER7 yet, this will be fixed later.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: bbc01ca7f265f2c5be8aee7c9ce1d10aa26063f5
https://github.com/qemu/qemu/commit/bbc01ca7f265f2c5be8aee7c9ce1d10aa26063f5
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu-models.c
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Merge 970FX and 970MP into a single 970 class
The differences between classes were:
1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
2. check_pow() callback, HID0 format is the same so should be the same
0x01C00000 which means "deep nap", "doze" and "nap" bits set;
3. LPCR - 970 does not have it but 970MP had one (by mistake).
This fixes wrong differences and makes one 970 class.
This fixes wrong registration of LPCR which is not present on 970.
This defines HID0 bits and uses them in check_pow_970().
This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to
970 class as we do not emulate hypervisor in QEMU anyway.
This does not remove check_pow_970FX now as it is still used by POWER5+
class, this will be addressed later.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 42382f624478adcba7ca14982e46e804831cbf7d
https://github.com/qemu/qemu/commit/42382f624478adcba7ca14982e46e804831cbf7d
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Refactor PPC970
This splits one init_proc_970() into a set of small helpers. Later
init_proc_970() will be generalized and will call different set of helpers
depending on the current CPU class.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: eb16dd9cc98694cdd904770a82267d5bbfc8f8af
https://github.com/qemu/qemu/commit/eb16dd9cc98694cdd904770a82267d5bbfc8f8af
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Make UCTRL a mirror of CTRL
This changes UCTRL SPR to read from its supermode copy.
This enables reading from UCTRL in user mode.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: fd51ff6328e3d981582436d1040f648c8da4a41f
https://github.com/qemu/qemu/commit/fd51ff6328e3d981582436d1040f648c8da4a41f
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Copy and split gen_spr_7xx() for 970
This stops using 7xx common SPRs init function and adds separate set
of helpers for 970.
This does not copy ICTC SPR as neither 970 manual nor PowerISA mention it.
This defines 970/book3s PMU SPRs constants as they differs from the ones
used for 7XX.
This creates 2 helpers for PMU SPRs, one for supermode privileged SPRs and
one for user privileged SPRs as "sup" versions can be shared across
the family while "user" versions will behave different starting POWER8
(which will be addressed later).
This allows writing to Uxxxx SPRs from supermode. spr_write_ureg() is
implemented for this as a copy of already existing spr_read_ureg().
This allows writing to supervisor's SIAR - it used to be disabled
when gen_spr_7xx() was used.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 75b9c321f44c13ccf1ba13eafc756b1a5d8f5eb1
https://github.com/qemu/qemu/commit/75b9c321f44c13ccf1ba13eafc756b1a5d8f5eb1
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add "POWER" prefix to MMCRA PMU registers
Since we started adding "POWER" prefix to 64bit PMU SPRs, let's finish
the transition and fix MMCRA and define a supermode version of it.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 077850b037eea63d9b01db96dd0cb65a46dd0f0f
https://github.com/qemu/qemu/commit/077850b037eea63d9b01db96dd0cb65a46dd0f0f
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family
MMCR0, MMCR1, MMCRA, PMC1..6, SIAR, SDAR are defined for 970 and PowerISA
CPUs. Since we are building common infrastructure for SPRs intialization
to share it between 970 and POWER5+/7/..., let's add missing SPRs to
the 970 family. Later rework of CPU class initialization will use those
for all PowerISA CPUs.
This adds new SPRs and enables writing to Uxxxx SPRs from supermode.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: c36c97f8804bbc2cd731f37a159ecdf618600871
https://github.com/qemu/qemu/commit/c36c97f8804bbc2cd731f37a159ecdf618600871
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add PMC7/8 to 970 class
Compared to PowerISA-compliant CPUs, 970 family has most of them plus
PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
Since we are changing SPRs for Book3s/970 families, let's add them too.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: ba881002194f61598aa8bd33c98a471210e904ef
https://github.com/qemu/qemu/commit/ba881002194f61598aa8bd33c98a471210e904ef
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add HID4 SPR for PPC970
Previously LPCR was registered for the 970 class which was wrong as
it does not have LPCR. Instead, HID4 is used which this patch registers.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 7488d481ce53a546512c959b1a6b0316aaed1f34
https://github.com/qemu/qemu/commit/7488d481ce53a546512c959b1a6b0316aaed1f34
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Introduce and reuse generalized init_proc_book3s_64()
At the moment every POWER CPU family has its own init_proc_POWERX function.
E500 already has common init function so we try to do the same thing.
This introduces BOOK3S_CPU_TYPE enum with 2 values - 970 and POWER5+.
This introduces generalized init_proc_book3s_64() which accepts a CPU type
as a parameter.
This uses new init function for 970 and POWER5+ CPU classes.
970 and POWER5+ use the same CPU class initialization except 3 things:
1. logical partitioning is controlled by LPCR (POWER5+) and HID4 (970)
SPRs;
2. 970 does not have EAR (External Access Register) SPR and PowerISA 2.03
defines one so keep it only for POWER5+;
3. POWER5+ does not have ALTIVEC so insns_flags does not have PPC_ALTIVEC
flag set and gen_spr_book3s_altivec() won't init ALTIVEC for POWER5+.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 90618f4f4d1e7b5b9fe40834646adac1e21d1b07
https://github.com/qemu/qemu/commit/90618f4f4d1e7b5b9fe40834646adac1e21d1b07
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Remove check_pow_970FX
After merging 970s into one class, check_pow_970() is used for all of them.
Since POWER5+ is no different in the matter of supported power modes,
let's use the same check_pow() callback for POWER5+ too,
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 83cc6f8c2f134ccff1a41ed86bbe3bc305e0c334
https://github.com/qemu/qemu/commit/83cc6f8c2f134ccff1a41ed86bbe3bc305e0c334
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Enable PMU SPRs migration
This enabled PMU SPRs migration by hooking hypv privileged versions with
"KVM one reg" IDs.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e61716aa9a4f7745e3fc0be3f1613f1eef4b47f9
https://github.com/qemu/qemu/commit/e61716aa9a4f7745e3fc0be3f1613f1eef4b47f9
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers
This moves PIR/PURR/SPURR SPRs to helpers. Later these helpers will be
called from generalized init_proc_book3s_64().
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 768167abb91ba59a5395c18d18f5c6f82c16e58f
https://github.com/qemu/qemu/commit/768167abb91ba59a5395c18d18f5c6f82c16e58f
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Move POWER8 TCE Address control (TAR) to a helper
This moves TAR SPR to a helper. Later this helper will be
called from generalized init_proc_book3s_64().
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 5db7d4faa328243153ddfe2e307f8d2b9ec20466
https://github.com/qemu/qemu/commit/5db7d4faa328243153ddfe2e307f8d2b9ec20466
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers
This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers
will be called from generalized init_proc_book3s_64().
This switches init_proc_POWER7() to use generalized gen_spr_book3s_common()
which registers CRTL SPR under slightly different names. No change in
behaviour or non-debug output is expected.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 6a1eed3f49e0fc5ef94906c0eab5314bc32bc8ae
https://github.com/qemu/qemu/commit/6a1eed3f49e0fc5ef94906c0eab5314bc32bc8ae
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8
This replaces VRSAVE registration and vscr_init() call with
gen_spr_book3s_altivec() which is generic and does the same thing if
insns_flags has PPC_ALTIVEC bit set (which POWER7/8 have set).
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 7fc2db18ce33994e59ab019ff66308906b3c0170
https://github.com/qemu/qemu/commit/7fc2db18ce33994e59ab019ff66308906b3c0170
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Make use of gen_spr_power5p_lpar() for POWER7/8
This makes use of generic gen_spr_power5p_lpar() which registers LPCR SPR.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 5881c296b98000f78979b2b9e9fca96543577a05
https://github.com/qemu/qemu/commit/5881c296b98000f78979b2b9e9fca96543577a05
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Switch POWER7/8 classes to use correct PMU SPRs
This replaces gen_spr_7xx() call (which registers 32bit SPRs) with
gen_spr_book3s_pmu() call.
This removes SPR_7XX_PMC5/6 as they are for 32bit and gen_spr_book3s_pmu()
already registers correct PMC5/6 SPRs.
This removes explicit MMCRA registration as gen_spr_book3s_pmu() does it
anyway.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: a242881405811ec6e6134452311f1cd1896c8ada
https://github.com/qemu/qemu/commit/a242881405811ec6e6134452311f1cd1896c8ada
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Refactor class init for POWER7/8
This extends init_proc_book3s_64 to support POWER7 and POWER8.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: d1a721ab816d1b954c0988aafdec4e109b953a9f
https://github.com/qemu/qemu/commit/d1a721ab816d1b954c0988aafdec4e109b953a9f
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add POWER8's TIR SPR
This adds TIR (Thread Identification Register) SPR first defined for server
CPUs in PowerISA 2.07.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 7019cb3d883c5fdd8e4e75d753eded288d94b592
https://github.com/qemu/qemu/commit/7019cb3d883c5fdd8e4e75d753eded288d94b592
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/excp_helper.c
M target-ppc/helper.h
M target-ppc/misc_helper.c
M target-ppc/translate.c
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add POWER8's FSCR SPR
This adds an FSCR (Facility Status and Control Register) SPR. This defines
names for FSCR bits.
This defines new exception type - POWERPC_EXCP_FU - "facility unavailable" (FU).
This registers an interrupt vector for it at 0xF60 as PowerISA defines.
This adds a TCG helper_fscr_facility_check() helper to raise an exception
if the facility is not enabled. It updates the interrupt cause field
in FSCR. This adds a TCG translation block generation code. The helper
may be used for HFSCR too as it has the same format.
The helper raising FU exceptions is not used by this patch but will be
in the next ones.
This adds gen_update_current_nip() to update NIP in DisasContext.
This helper is not used now and will be called before checking for
a condition for throwing an FU exception.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 45ed0be146b7433d1123f09eb1a984210a311625
https://github.com/qemu/qemu/commit/45ed0be146b7433d1123f09eb1a984210a311625
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Enable FSCR facility check for TAR
This makes user-privileged read/write fail if TAR facility is not enabled
in FSCR.
Since this is the very first check for enabled in FSCR facility,
this also adds gen_fscr_facility_check() for using in spr_write_tar()/
spr_read_tar().
This enables TAR in FSCR for user mode unconditionally.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 70c5340744f044d2195216d0e3c7c0c554dbd7ca
https://github.com/qemu/qemu/commit/70c5340744f044d2195216d0e3c7c0c554dbd7ca
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add POWER8's MMCR2/MMCRS SPRs
This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: cdcdda27fc843873875e7e444e0164ba2a5e9942
https://github.com/qemu/qemu/commit/cdcdda27fc843873875e7e444e0164ba2a5e9942
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/helper.h
M target-ppc/misc_helper.c
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add POWER8's TM SPRs
This adds TM (Transactional Memory) SPRs.
This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
Since this is not the only register like that and their numbers go
consequently, it makes sense to generalize the helpers.
This adds a gen_msr_facility_check() helper which purpose is to generate
the Facility Unavailable exception if the facility is disabled.
It is a copy of gen_fscr_facility_check() but it checks for enabled
facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause
in FSCR/HFSCR (whichever is passed to the helper).
This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32
which are used for TM SPRs.
This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class'
msr_mask.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 80b3f79b999a334b277137f698c43e7730da4224
https://github.com/qemu/qemu/commit/80b3f79b999a334b277137f698c43e7730da4224
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/kvm.c
M target-ppc/machine.c
Log Message:
-----------
KVM: target-ppc: Enable TM state migration
This adds migration support for registers saved before Transactional
Memory (TM) transaction started.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 4ee4a03b38685be863803e52d9b00ffbc7ce9a22
https://github.com/qemu/qemu/commit/4ee4a03b38685be863803e52d9b00ffbc7ce9a22
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs
POWER8 supports Event-Based Branch Facility (EBB). It is controlled via
set of SPRs access to which should generate an "Facility Unavailable"
interrupt if the facilities are not enabled in FSCR for problem state.
This adds EBB SPRs.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 7303f83db61c211eb59823cd955929a46879a8bc
https://github.com/qemu/qemu/commit/7303f83db61c211eb59823cd955929a46879a8bc
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Enable PPR and VRSAVE SPRs migration
This hooks SPR with their "KVM set_one_reg" counterparts which enables
their migration.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: cd9adfdd7755f053aea1ffc8e1df7b9b022174ff
https://github.com/qemu/qemu/commit/cd9adfdd7755f053aea1ffc8e1df7b9b022174ff
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Enable DABRX SPR and limit it to <=POWER7
This adds DABRX SPR.
As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
have them (as it implements more powerful facility instead), this limits
DABR/DABRX registration by POWER7 (inclusive).
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: c4015bbd502d670d88e5689e1143e36ea097c76f
https://github.com/qemu/qemu/commit/c4015bbd502d670d88e5689e1143e36ea097c76f
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr_hcall: Split h_set_mode()
This moves H_SET_MODE_RESOURCE_LE handler to a separate function
as there are other "resources" coming and this is going to become ugly.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: d5ac4f543352c3412172fb72256137defb13a4b1
https://github.com/qemu/qemu/commit/d5ac4f543352c3412172fb72256137defb13a4b1
Author: Alexey Kardashevskiy <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
M target-ppc/cpu.h
M target-ppc/excp_helper.c
Log Message:
-----------
spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
This defines AIL flags for LPCR special register.
This changes @excp_prefix according to the mode, takes effect in TCG.
This turns support of a new capability PPC2_ISA207S flag for TCG.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: a70daba3771e96cc6b8fd3d11ed297ab13717018
https://github.com/qemu/qemu/commit/a70daba3771e96cc6b8fd3d11ed297ab13717018
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user: Tell guest about big host page sizes
We tell the guest its page size via AUX vectors. The guest process then uses
this page size as information on which boundaries it can mmap() things.
However, if the host has a bigger page size granularity than the guest, it can
not fulfill these mmap() requests - which falls apart when MAP_FIXED is passed
to mmap.
So in that case, let the guest know that we're running on a bigger page size
granularity than the target would require.
This fixes running qemu-ppc (TARGET_PAGE_SIZE=4k) on a 64k page size ppc64 host
for me.
Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 748abce94fafd630a5e33518e146baa3da463c48
https://github.com/qemu/qemu/commit/748abce94fafd630a5e33518e146baa3da463c48
Author: Eduardo Habkost <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Create SPAPRMachine struct
Signed-off-by: Eduardo Habkost <address@hidden>
Tested-by: Aneesh Kumar K.V <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 23825581d7c106db28f902d09b9a7274b3c8dede
https://github.com/qemu/qemu/commit/23825581d7c106db28f902d09b9a7274b3c8dede
Author: Eduardo Habkost <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Add kvm-type property
The kvm-type machine option was left out when MachineState was
introduced, preventing the kvm-type option from being used. Add the
missing property to the sPAPR machine class, so it can be used.
Signed-off-by: Eduardo Habkost <address@hidden>
Tested-by: Aneesh Kumar K.V <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e223bcad6e0952d0e205f42b411e96e42262eded
https://github.com/qemu/qemu/commit/e223bcad6e0952d0e205f42b411e96e42262eded
Author: Tristan Gingold <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/fpu_helper.c
Log Message:
-----------
powerpc: use float64 for frsqrte
Remove the code that reduce the result to float32 as the frsqrte
instruction is defined to return a double-precision estimate of
the reciprocal square root.
Although reducing the fractional part is harmless (as the estimation
must have at least 12 bits of precision according to the old PEM),
reducing the exponent range is not correct.
Signed-off-by: Tristan Gingold <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: d13fc32ecf8d810ec9894a35e1cfae81f7d88039
https://github.com/qemu/qemu/commit/d13fc32ecf8d810ec9894a35e1cfae81f7d88039
Author: Alexander Graf <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
PPC: KVM: Make pv hcall endian agnostic
There were a few revisions of the Linux kernel that incorrectly swapped
the hcall instructions when they saw ePAPR compliant hypercalls.
We already have fixups for those in place when running with PR KVM, but
HV KVM and systems that don't implement hypercalls at all are still broken
because they fall back to the QEMU implementation of fallback hypercalls.
So let's make the fallback hypercall instruction path endian agnostic. This
only really works well for 64bit guests, but I don't think there are any 32bit
systems left that don't implement real pv hcall support, so we'll never get
into this code path.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9dbae97723e964692364fb43012c6fa5448a661f
https://github.com/qemu/qemu/commit/9dbae97723e964692364fb43012c6fa5448a661f
Author: Badari Pulavarty <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_pci.c
M include/hw/ppc/xics.h
Log Message:
-----------
spapr_pci: Advertise MSI quota
Hotplug of multiple disks fails due to MSI vector quota check.
Number of MSI vectors default to 8 allowing only 4 devices.
This happens on RHEL6.5 guest. RHEL7 and SLES11 guests fallback
to INTX.
One way to workaround the issue is to increase total MSIs,
so that MSI quota check allows us to hotplug multiple disks.
This sets the quota to the maximum number of interupts XICS has
which is 1024 now (XICS_IRQS). This moves XICS_IRQS from spapr.c
to xics.h for wider visibility.
Signed-off-by: Badari Pulavarty <address@hidden>
[aik: put XICS_IRQS=1024 instead of 64i, fixed endianness and size]
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: af44da87e926ff64260b95f4350d338c4fc113ca
https://github.com/qemu/qemu/commit/af44da87e926ff64260b95f4350d338c4fc113ca
Author: Peter Maydell <address@hidden>
Date: 2014-06-16 (Mon, 16 Jun 2014)
Changed paths:
M .gitmodules
M Makefile.target
M configure
M default-configs/ppc-linux-user.mak
M default-configs/ppc-softmmu.mak
M default-configs/ppc64-linux-user.mak
M default-configs/ppc64-softmmu.mak
M default-configs/ppc64abi32-linux-user.mak
A default-configs/ppc64le-linux-user.mak
M default-configs/ppcemb-softmmu.mak
M disas.c
M dump.c
M hw/ide/macio.c
M hw/intc/openpic.c
M hw/intc/openpic_kvm.c
M hw/misc/macio/mac_dbdma.c
M hw/misc/macio/macio.c
M hw/net/fsl_etsec/rings.c
M hw/nvram/spapr_nvram.c
M hw/pci-host/ppce500.c
M hw/ppc/e500.c
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M hw/ppc/ppc.c
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M include/elf.h
M include/hw/pci-host/spapr.h
M include/hw/ppc/mac_dbdma.h
M include/hw/ppc/ppc.h
M include/hw/ppc/spapr.h
M include/hw/ppc/xics.h
A include/libdecnumber/dconfig.h
A include/libdecnumber/decContext.h
A include/libdecnumber/decDPD.h
A include/libdecnumber/decNumber.h
A include/libdecnumber/decNumberLocal.h
A include/libdecnumber/dpd/decimal128.h
A include/libdecnumber/dpd/decimal128Local.h
A include/libdecnumber/dpd/decimal32.h
A include/libdecnumber/dpd/decimal64.h
M include/qemu/aes.h
A include/sysemu/dump-arch.h
M include/sysemu/dump.h
A libdecnumber/decContext.c
A libdecnumber/decNumber.c
A libdecnumber/dpd/decimal128.c
A libdecnumber/dpd/decimal128Local.h
A libdecnumber/dpd/decimal32.c
A libdecnumber/dpd/decimal64.c
M linux-headers/asm-arm/kvm.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-mips/kvm.h
M linux-headers/asm-powerpc/kvm.h
M linux-headers/asm-powerpc/kvm_para.h
M linux-headers/linux/kvm.h
A linux-headers/linux/psci.h
M linux-user/elfload.c
M linux-user/main.c
M linux-user/ppc/syscall.h
M monitor.c
M pc-bios/README
A pc-bios/u-boot.e500
M roms/Makefile
A roms/u-boot
M scripts/update-linux-headers.sh
M stubs/dump.c
M target-arm/crypto_helper.c
M target-i386/ops_sse.h
M target-ppc/Makefile.objs
M target-ppc/arch_dump.c
M target-ppc/cpu-models.c
M target-ppc/cpu-models.h
M target-ppc/cpu-qom.h
M target-ppc/cpu.h
A target-ppc/dfp_helper.c
M target-ppc/excp_helper.c
M target-ppc/fpu_helper.c
M target-ppc/gdbstub.c
M target-ppc/helper.h
M target-ppc/int_helper.c
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
M target-ppc/machine.c
M target-ppc/mem_helper.c
M target-ppc/misc_helper.c
M target-ppc/mmu_helper.c
M target-ppc/translate.c
M target-ppc/translate_init.c
M trace-events
M util/aes.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream'
into staging
Patch queue for ppc - 2014-06-16
This pull request brings a lot of fun things. Among others we have
- e500: u-boot firmware support
- sPAPR: magic page enablement
- sPAPR: add "compat" CPU option to support older guests
- sPAPR: refactorings in preparation for VFIO
- POWER8 live migration
- mac99: expose bus frequency
- little endian core dump, gdb and disas support
- new ppc64le-linux-user target
- DFP emulation
- bug fixes
# gpg: Signature made Mon 16 Jun 2014 12:28:32 BST using RSA key ID 03FEDC60
# gpg: Can't check signature: public key not found
* remotes/agraf/tags/signed-ppc-for-upstream: (156 commits)
spapr_pci: Advertise MSI quota
PPC: KVM: Make pv hcall endian agnostic
powerpc: use float64 for frsqrte
spapr: Add kvm-type property
spapr: Create SPAPRMachine struct
linux-user: Tell guest about big host page sizes
spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
spapr_hcall: Split h_set_mode()
target-ppc: Enable DABRX SPR and limit it to <=POWER7
target-ppc: Enable PPR and VRSAVE SPRs migration
target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs
KVM: target-ppc: Enable TM state migration
target-ppc: Add POWER8's TM SPRs
target-ppc: Add POWER8's MMCR2/MMCRS SPRs
target-ppc: Enable FSCR facility check for TAR
target-ppc: Add POWER8's FSCR SPR
target-ppc: Add POWER8's TIR SPR
target-ppc: Refactor class init for POWER7/8
target-ppc: Switch POWER7/8 classes to use correct PMU SPRs
target-ppc: Make use of gen_spr_power5p_lpar() for POWER7/8
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/f27701510cdc...af44da87e926
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] e13951: target-ppc: Fix target_disas,
GitHub <=