Re: CXL Namespaces of ACPI disappearing in Qemu demo

[Jonathan Cameron]

On Wed, 23 Aug 2023 15:44:35 -0400
Gregory Price <gregory.price@memverge.com> wrote:

> On Tue, Aug 22, 2023 at 03:22:02PM +0800, Yuquan Wang wrote:
> > Hi, Gregory
> > I am sorry to disturb you, but there was still an ignored problem about 
> > CXL, 
> > Although I had sent an email to jonathan (maybe he is busy recently so he 
> > forgot to reply),  
> > the Link is : 
> > https://lists.nongnu.org/archive/html/qemu-arm/2023-08/msg00278.html 
> > 
> > Maybe the core question is that how should we use CXL components with a 
> > standard PCIe system：
> > 1) In Qemu, since the boards or machines in qemu can only use pxb-cxl 
> > (attached on pcie.0) to add
> > cxl host bridge, therefore, users should avoid to assign an occupied bus 
> > number by other devices
> > to pxb-cxl.
> > 
> > 2) In real hardware, CXL components should use independent CXL root/tree 
> > (ACPI0017&ACPI0016)
> > to separate from the namespace of default pcie root/domain.
> > 
> > I would be grateful if you have some free time to help check this issue : )
> >   
> 
> Generally speaking, ACPI questions are outside the scope of my
> knowledge, but to the extent that i have debugged QEMU for CXL I can say
> that #1 is correct - the host bridge adapter should not share PCI bus
> id's with anything else or you will have issues.  This can be
> frustrating if you don't know what the magic numbers are.
> 
> for my work, i have been using this when i need to attach two pxb-cxl
> deivces
> 
> qemu-system-x86_64 \
> -drive file=./cxl.qcow2,format=qcow2,index=0,media=disk,id=hd \
> -m 4G,slots=4,maxmem=8G \
> -smp 4 \
> -machine type=q35,cxl=on,hmat=on \
> -device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 \
> -device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=191 \
> 
> 
> In regards to real hardware, I'm honestly not knowledgable enough about
> ACPI or hardware to provide an intelligible answer unfortunately.
> 
> ~Gregory

One additional thing to note. Nothing stops you putting a PCI device on a CXL
root port, or downstream switch port.  Some of the reporting is probably wrong
at the moment, but I've messed around with NVME below one and that 'works' fine
as Linux doesn't read the relevant registers anyway.

Jonathan