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[PATCH v2 5/9] exec/memattrs: Remove target_tlb_bit*
From: |
Richard Henderson |
Subject: |
[PATCH v2 5/9] exec/memattrs: Remove target_tlb_bit* |
Date: |
Wed, 21 Jun 2023 14:18:58 +0200 |
These fields are no longer used since 937f224559.
Target specific extensions to the page tables should be done
with TARGET_PAGE_ENTRY_EXTRA.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memattrs.h | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 9fb98bc1ef..1bd7b6c5ca 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -47,16 +47,6 @@ typedef struct MemTxAttrs {
unsigned int requester_id:16;
/* Invert endianness for this page */
unsigned int byte_swap:1;
- /*
- * The following are target-specific page-table bits. These are not
- * related to actual memory transactions at all. However, this structure
- * is part of the tlb_fill interface, cached in the cputlb structure,
- * and has unused bits. These fields will be read by target-specific
- * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN.
- */
- unsigned int target_tlb_bit0 : 1;
- unsigned int target_tlb_bit1 : 1;
- unsigned int target_tlb_bit2 : 1;
} MemTxAttrs;
/* Bus masters which don't specify any attributes will get this,
--
2.34.1
- [PATCH v2 0/9] {tcg,aarch64}: Add TLB_CHECK_ALIGNED, Richard Henderson, 2023/06/21
- [PATCH v2 1/9] accel/tcg: Store some tlb flags in CPUTLBEntryFull, Richard Henderson, 2023/06/21
- [PATCH v2 4/9] target/arm: Support 32-byte alignment in pow2_align, Richard Henderson, 2023/06/21
- [PATCH v2 2/9] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK, Richard Henderson, 2023/06/21
- [PATCH v2 5/9] exec/memattrs: Remove target_tlb_bit*,
Richard Henderson <=
- [PATCH v2 9/9] target/arm: Do memory type alignment check when translation enabled, Richard Henderson, 2023/06/21
- [PATCH v2 7/9] accel/tcg: Add TLB_CHECK_ALIGNED, Richard Henderson, 2023/06/21
- [PATCH v2 8/9] target/arm: Do memory type alignment check when translation disabled, Richard Henderson, 2023/06/21
- [PATCH v2 3/9] accel/tcg: Renumber TLB_DISCARD_WRITE, Richard Henderson, 2023/06/21
- [PATCH v2 6/9] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull, Richard Henderson, 2023/06/21