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[PATCH v3 05/17] include/hw/core: Create struct CPUJumpCache
From: |
Richard Henderson |
Subject: |
[PATCH v3 05/17] include/hw/core: Create struct CPUJumpCache |
Date: |
Mon, 22 Aug 2022 16:23:26 -0700 |
Wrap the bare TranslationBlock pointer into a structure.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 8 ++++++--
accel/tcg/cpu-exec.c | 9 ++++++---
accel/tcg/cputlb.c | 2 +-
accel/tcg/translate-all.c | 4 ++--
4 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 500503da13..8edef14199 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -233,6 +233,10 @@ struct hvf_vcpu_state;
#define TB_JMP_CACHE_BITS 12
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
+typedef struct {
+ TranslationBlock *tb;
+} CPUJumpCache;
+
/* work queue */
/* The union type allows passing of 64 bit target pointers on 32 bit
@@ -362,7 +366,7 @@ struct CPUState {
IcountDecr *icount_decr_ptr;
/* Accessed in parallel; all accesses must be atomic */
- TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
+ CPUJumpCache tb_jmp_cache[TB_JMP_CACHE_SIZE];
struct GDBRegisterState *gdb_regs;
int gdb_num_regs;
@@ -453,7 +457,7 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
unsigned int i;
for (i = 0; i < TB_JMP_CACHE_SIZE; i++) {
- qatomic_set(&cpu->tb_jmp_cache[i], NULL);
+ qatomic_set(&cpu->tb_jmp_cache[i].tb, NULL);
}
}
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index b1fd962718..3f8e4bbbc8 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -243,7 +243,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu,
target_ulong pc,
tcg_debug_assert(!(cflags & CF_INVALID));
hash = tb_jmp_cache_hash_func(pc);
- tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
+ tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb);
if (likely(tb &&
tb->pc == pc &&
@@ -257,7 +257,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu,
target_ulong pc,
if (tb == NULL) {
return NULL;
}
- qatomic_set(&cpu->tb_jmp_cache[hash], tb);
+ qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb);
return tb;
}
@@ -978,6 +978,8 @@ int cpu_exec(CPUState *cpu)
tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
if (tb == NULL) {
+ uint32_t h;
+
mmap_lock();
tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
mmap_unlock();
@@ -985,7 +987,8 @@ int cpu_exec(CPUState *cpu)
* We add the TB in the virtual pc hash table
* for the fast lookup
*/
- qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)],
tb);
+ h = tb_jmp_cache_hash_func(pc);
+ qatomic_set(&cpu->tb_jmp_cache[h].tb, tb);
}
#ifndef CONFIG_USER_ONLY
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 8b81b07b79..a8afe1ab9f 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -103,7 +103,7 @@ static void tb_jmp_cache_clear_page(CPUState *cpu,
target_ulong page_addr)
unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr);
for (i = 0; i < TB_JMP_PAGE_SIZE; i++) {
- qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL);
+ qatomic_set(&cpu->tb_jmp_cache[i0 + i].tb, NULL);
}
}
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 20f00f4335..c2745f14a6 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1187,8 +1187,8 @@ static void do_tb_phys_invalidate(TranslationBlock *tb,
bool rm_from_page_list)
/* remove the TB from the hash list */
h = tb_jmp_cache_hash_func(tb->pc);
CPU_FOREACH(cpu) {
- if (qatomic_read(&cpu->tb_jmp_cache[h]) == tb) {
- qatomic_set(&cpu->tb_jmp_cache[h], NULL);
+ if (qatomic_read(&cpu->tb_jmp_cache[h].tb) == tb) {
+ qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL);
}
}
--
2.34.1
- [PATCH v3 00/17] accel/tcg + target/arm: pc-relative translation, Richard Henderson, 2022/08/22
- [PATCH v3 01/17] accel/tcg: Remove PageDesc code_bitmap, Richard Henderson, 2022/08/22
- [PATCH v3 03/17] accel/tcg: Use DisasContextBase in plugin_gen_tb_start, Richard Henderson, 2022/08/22
- [PATCH v3 04/17] accel/tcg: Do not align tb->page_addr[0], Richard Henderson, 2022/08/22
- [PATCH v3 02/17] accel/tcg: Use bool for page_find_alloc, Richard Henderson, 2022/08/22
- [PATCH v3 05/17] include/hw/core: Create struct CPUJumpCache,
Richard Henderson <=
- [PATCH v3 13/17] target/arm: Change gen_exception_internal to work on displacements, Richard Henderson, 2022/08/22
- [PATCH v3 14/17] target/arm: Change gen_jmp* to work on displacements, Richard Henderson, 2022/08/22
- [PATCH v3 11/17] target/arm: Change gen_*set_pc_im to gen_*update_pc, Richard Henderson, 2022/08/22
- [PATCH v3 15/17] target/arm: Introduce gen_pc_plus_diff for aarch64, Richard Henderson, 2022/08/22
- [PATCH v3 07/17] accel/tcg: Introduce TARGET_TB_PCREL, Richard Henderson, 2022/08/22
- [PATCH v3 08/17] accel/tcg: Split log_cpu_exec into inline and slow path, Richard Henderson, 2022/08/22
- [PATCH v3 12/17] target/arm: Change gen_exception_insn* to work on displacements, Richard Henderson, 2022/08/22
- [PATCH v3 09/17] target/arm: Introduce curr_insn_len, Richard Henderson, 2022/08/22
- [PATCH v3 06/17] accel/tcg: Introduce tb_pc and tb_pc_log, Richard Henderson, 2022/08/22
- [PATCH v3 10/17] target/arm: Change gen_goto_tb to work on displacements, Richard Henderson, 2022/08/22