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[PATCH 6/7] pci: designware: correct host's class_id
From: |
Ben Dooks |
Subject: |
[PATCH 6/7] pci: designware: correct host's class_id |
Date: |
Wed, 13 Jul 2022 17:54:48 +0100 |
This is a host to pcie bridge, so use PCI_CLASS_BRIDGE_HOST
for the class.
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
hw/pci-host/designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index b5d5b2b8a5..a47ae48071 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -615,7 +615,7 @@ static void designware_pcie_root_class_init(ObjectClass
*klass, void *data)
k->vendor_id = PCI_VENDOR_ID_SYNOPSYS;
k->device_id = 0xABCD;
k->revision = 0;
- k->class_id = PCI_CLASS_BRIDGE_PCI;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
k->is_bridge = true;
k->exit = pci_bridge_exitfn;
k->realize = designware_pcie_root_realize;
--
2.35.1
- updates for designware pci-host, Ben Dooks, 2022/07/13
- [PATCH 1/7] pci: designware: add 64-bit viewport limit, Ben Dooks, 2022/07/13
- [PATCH 3/7] pci: designware: clamp viewport index, Ben Dooks, 2022/07/13
- [PATCH 6/7] pci: designware: correct host's class_id,
Ben Dooks <=
- [PATCH 7/7] pci: designware: add initial tracing events, Ben Dooks, 2022/07/13
- [PATCH 5/7] pci: designware: move msi to entry 5, Ben Dooks, 2022/07/13
- [PATCH 2/7] pci: designware: fix DESIGNWARE_PCIE_ATU_UPPER_TARGET, Ben Dooks, 2022/07/13
- [PATCH 4/7] pci: designware: ignore new bits in ATU CR1, Ben Dooks, 2022/07/13
- Re: updates for designware pci-host, Ben Dooks, 2022/07/27