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[PATCH 1/7] pci: designware: add 64-bit viewport limit
From: |
Ben Dooks |
Subject: |
[PATCH 1/7] pci: designware: add 64-bit viewport limit |
Date: |
Wed, 13 Jul 2022 17:54:43 +0100 |
Versions 4 and above add support for 64-bit viewport
limit. Add support for the DESIGNWARE_PCIE_ATU_UPPER_LIMIT
regiser where supported.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
hw/pci-host/designware.c | 22 +++++++++++++++++-----
include/hw/pci-host/designware.h | 2 +-
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index bde3a343a2..296f1b9760 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -54,6 +54,7 @@
#define DESIGNWARE_PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
+#define DESIGNWARE_PCIE_ATU_UPPER_LIMIT 0x924
#define DESIGNWARE_PCIE_IRQ_MSI 3
@@ -196,6 +197,10 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_t
address, int len)
val = viewport->target >> 32;
break;
+ case DESIGNWARE_PCIE_ATU_UPPER_LIMIT:
+ val = viewport->limit >> 32;
+ break;
+
case DESIGNWARE_PCIE_ATU_LIMIT:
val = viewport->limit;
break;
@@ -269,7 +274,7 @@ static void
designware_pcie_update_viewport(DesignwarePCIERoot *root,
{
const uint64_t target = viewport->target;
const uint64_t base = viewport->base;
- const uint64_t size = (uint64_t)viewport->limit - base + 1;
+ const uint64_t size = viewport->limit - base + 1;
const bool enabled = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE;
MemoryRegion *current, *other;
@@ -363,14 +368,21 @@ static void designware_pcie_root_config_write(PCIDevice
*d, uint32_t address,
viewport->target |= val;
break;
+ case DESIGNWARE_PCIE_ATU_UPPER_LIMIT:
+ viewport->limit &= 0x00000000FFFFFFFFUL;
+ viewport->limit |= (uint64_t)val << 32;
+ break;
+
case DESIGNWARE_PCIE_ATU_LIMIT:
- viewport->limit = val;
+ viewport->limit = 0xFFFFFFFF00000000ULL;
+ viewport->limit |= val;
break;
case DESIGNWARE_PCIE_ATU_CR1:
viewport->cr[0] = val;
break;
case DESIGNWARE_PCIE_ATU_CR2:
+ //printf("CR2: value %08x\n", val);
viewport->cr[1] = val;
designware_pcie_update_viewport(root, viewport);
break;
@@ -429,7 +441,7 @@ static void designware_pcie_root_realize(PCIDevice *dev,
Error **errp)
viewport->inbound = true;
viewport->base = 0x0000000000000000ULL;
viewport->target = 0x0000000000000000ULL;
- viewport->limit = UINT32_MAX;
+ viewport->limit = UINT64_MAX-1;
viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM;
source = &host->pci.address_space_root;
@@ -453,7 +465,7 @@ static void designware_pcie_root_realize(PCIDevice *dev,
Error **errp)
viewport->inbound = false;
viewport->base = 0x0000000000000000ULL;
viewport->target = 0x0000000000000000ULL;
- viewport->limit = UINT32_MAX;
+ viewport->limit = UINT64_MAX-1;
viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM;
destination = &host->pci.memory;
@@ -560,7 +572,7 @@ static const VMStateDescription
vmstate_designware_pcie_viewport = {
.fields = (VMStateField[]) {
VMSTATE_UINT64(base, DesignwarePCIEViewport),
VMSTATE_UINT64(target, DesignwarePCIEViewport),
- VMSTATE_UINT32(limit, DesignwarePCIEViewport),
+ VMSTATE_UINT64(limit, DesignwarePCIEViewport),
VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
VMSTATE_END_OF_LIST()
}
diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
index 6d9b51ae67..bd4dd49aec 100644
--- a/include/hw/pci-host/designware.h
+++ b/include/hw/pci-host/designware.h
@@ -44,7 +44,7 @@ typedef struct DesignwarePCIEViewport {
uint64_t base;
uint64_t target;
- uint32_t limit;
+ uint64_t limit;
uint32_t cr[2];
bool inbound;
--
2.35.1
- updates for designware pci-host, Ben Dooks, 2022/07/13
- [PATCH 1/7] pci: designware: add 64-bit viewport limit,
Ben Dooks <=
- [PATCH 3/7] pci: designware: clamp viewport index, Ben Dooks, 2022/07/13
- [PATCH 6/7] pci: designware: correct host's class_id, Ben Dooks, 2022/07/13
- [PATCH 7/7] pci: designware: add initial tracing events, Ben Dooks, 2022/07/13
- [PATCH 5/7] pci: designware: move msi to entry 5, Ben Dooks, 2022/07/13
- [PATCH 2/7] pci: designware: fix DESIGNWARE_PCIE_ATU_UPPER_TARGET, Ben Dooks, 2022/07/13
- [PATCH 4/7] pci: designware: ignore new bits in ATU CR1, Ben Dooks, 2022/07/13
- Re: updates for designware pci-host, Ben Dooks, 2022/07/27