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[PATCH v6 18/45] target/arm: Implement SME ZERO
From: |
Richard Henderson |
Subject: |
[PATCH v6 18/45] target/arm: Implement SME ZERO |
Date: |
Fri, 8 Jul 2022 20:45:13 +0530 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v4: Fix ZA[] comment in helper_sme_zero.
---
target/arm/helper-sme.h | 2 ++
target/arm/sme.decode | 4 ++++
target/arm/sme_helper.c | 25 +++++++++++++++++++++++++
target/arm/translate-sme.c | 13 +++++++++++++
4 files changed, 44 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 3bd48c235f..c4ee1f09e4 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -19,3 +19,5 @@
DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32)
+
+DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index c25c031a71..6e4483fdce 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -18,3 +18,7 @@
#
# This file is processed by scripts/decodetree.py
#
+
+### SME Misc
+
+ZERO 11000000 00 001 00000000000 imm:8
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index b215725594..eef2df73e1 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -59,3 +59,28 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i)
memset(env->zarray, 0, sizeof(env->zarray));
}
}
+
+void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
+{
+ uint32_t i;
+
+ /*
+ * Special case clearing the entire ZA space.
+ * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any
+ * parts of the ZA storage outside of SVL.
+ */
+ if (imm == 0xff) {
+ memset(env->zarray, 0, sizeof(env->zarray));
+ return;
+ }
+
+ /*
+ * Recall that ZAnH.D[m] is spread across ZA[n+8*m],
+ * so each row is discontiguous within ZA[].
+ */
+ for (i = 0; i < svl; i++) {
+ if (imm & (1 << (i % 8))) {
+ memset(&env->zarray[i], 0, svl);
+ }
+ }
+}
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 786c93fb2d..971504559b 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -33,3 +33,16 @@
*/
#include "decode-sme.c.inc"
+
+
+static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
+{
+ if (!dc_isar_feature(aa64_sme, s)) {
+ return false;
+ }
+ if (sme_za_enabled_check(s)) {
+ gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm),
+ tcg_constant_i32(streaming_vec_reg_size(s)));
+ }
+ return true;
+}
--
2.34.1
- [PATCH v6 10/45] target/arm: Mark string/histo/crypto as non-streaming, (continued)
- [PATCH v6 10/45] target/arm: Mark string/histo/crypto as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 07/45] target/arm: Mark PMULL, FMMLA as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 11/45] target/arm: Mark gather/scatter load/store as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 12/45] target/arm: Mark gather prefetch as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 14/45] target/arm: Mark LD1RO as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 15/45] target/arm: Add SME enablement checks, Richard Henderson, 2022/07/08
- [PATCH v6 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 16/45] target/arm: Handle SME in sve_access_check, Richard Henderson, 2022/07/08
- [PATCH v6 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL, Richard Henderson, 2022/07/08
- [PATCH v6 18/45] target/arm: Implement SME ZERO,
Richard Henderson <=
- [PATCH v6 19/45] target/arm: Implement SME MOVA, Richard Henderson, 2022/07/08
- [PATCH v6 20/45] target/arm: Implement SME LD1, ST1, Richard Henderson, 2022/07/08
- [PATCH v6 21/45] target/arm: Export unpredicated ld/st from translate-sve.c, Richard Henderson, 2022/07/08
- [PATCH v6 22/45] target/arm: Implement SME LDR, STR, Richard Henderson, 2022/07/08
- [PATCH v6 23/45] target/arm: Implement SME ADDHA, ADDVA, Richard Henderson, 2022/07/08
- [PATCH v6 24/45] target/arm: Implement FMOPA, FMOPS (non-widening), Richard Henderson, 2022/07/08
- [PATCH v6 25/45] target/arm: Implement BFMOPA, BFMOPS, Richard Henderson, 2022/07/08
- [PATCH v6 26/45] target/arm: Implement FMOPA, FMOPS (widening), Richard Henderson, 2022/07/08
- [PATCH v6 27/45] target/arm: Implement SME integer outer product, Richard Henderson, 2022/07/08
- [PATCH v6 28/45] target/arm: Implement PSEL, Richard Henderson, 2022/07/08