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[PATCH v6 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSS
From: |
Richard Henderson |
Subject: |
[PATCH v6 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming |
Date: |
Fri, 8 Jul 2022 20:45:01 +0530 |
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 3 ---
target/arm/translate-sve.c | 22 ++++++++++++----------
2 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index fa2b5cbf1a..4f515939d9 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -59,9 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register
(register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register
(scaled imm)
-FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA
-FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT
-FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP
FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b
result)
FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA
FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d6faec15fe..ae48040aa4 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1333,14 +1333,15 @@ static gen_helper_gvec_2 * const fexpa_fns[4] = {
NULL, gen_helper_sve_fexpa_h,
gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
};
-TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
- fexpa_fns[a->esz], a->rd, a->rn, 0)
+TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz,
+ fexpa_fns[a->esz], a->rd, a->rn, 0)
static gen_helper_gvec_3 * const ftssel_fns[4] = {
NULL, gen_helper_sve_ftssel_h,
gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d,
};
-TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz,
+ ftssel_fns[a->esz], a, 0)
/*
*** SVE Predicate Logical Operations Group
@@ -2536,7 +2537,8 @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
static gen_helper_gvec_3 * const compact_fns[4] = {
NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
};
-TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz,
+ compact_fns[a->esz], a, 0)
/* Call the helper that computes the ARM LastActiveElement pseudocode
* function, scaled by the element size. This includes the not found
@@ -6374,22 +6376,22 @@ static gen_helper_gvec_3 * const bext_fns[4] = {
gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
};
-TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
- bext_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bext_fns[a->esz], a, 0)
static gen_helper_gvec_3 * const bdep_fns[4] = {
gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
};
-TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
- bdep_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bdep_fns[a->esz], a, 0)
static gen_helper_gvec_3 * const bgrp_fns[4] = {
gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
};
-TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
- bgrp_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bgrp_fns[a->esz], a, 0)
static gen_helper_gvec_3 * const cadd_fns[4] = {
gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
--
2.34.1
- [PATCH v6 00/45] target/arm: Scalable Matrix Extension, Richard Henderson, 2022/07/08
- [PATCH v6 01/45] target/arm: Handle SME in aarch64_cpu_dump_state, Richard Henderson, 2022/07/08
- [PATCH v6 02/45] target/arm: Add infrastructure for disas_sme, Richard Henderson, 2022/07/08
- [PATCH v6 04/45] target/arm: Mark ADR as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active, Richard Henderson, 2022/07/08
- [PATCH v6 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 10/45] target/arm: Mark string/histo/crypto as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming,
Richard Henderson <=
- [PATCH v6 07/45] target/arm: Mark PMULL, FMMLA as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 11/45] target/arm: Mark gather/scatter load/store as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 12/45] target/arm: Mark gather prefetch as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 14/45] target/arm: Mark LD1RO as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 15/45] target/arm: Add SME enablement checks, Richard Henderson, 2022/07/08
- [PATCH v6 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming, Richard Henderson, 2022/07/08
- [PATCH v6 16/45] target/arm: Handle SME in sve_access_check, Richard Henderson, 2022/07/08
- [PATCH v6 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL, Richard Henderson, 2022/07/08
- [PATCH v6 18/45] target/arm: Implement SME ZERO, Richard Henderson, 2022/07/08
- [PATCH v6 19/45] target/arm: Implement SME MOVA, Richard Henderson, 2022/07/08