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[PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate
From: |
Richard Henderson |
Subject: |
[PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate |
Date: |
Sun, 3 Jul 2022 13:53:54 +0530 |
Rename the argument to is_secure_ptr, and introduce a
local variable is_secure with the value. We only write
back to the pointer toward the end of the function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index f76a8e931a..12288ac365 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -207,24 +207,26 @@ static bool ptw_attrs_are_device(CPUARMState *env,
ARMCacheAttrs cacheattrs)
/* Translate a S1 pagetable walk through S2 if needed. */
static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
- hwaddr addr, bool *is_secure,
+ hwaddr addr, bool *is_secure_ptr,
ARMMMUFaultInfo *fi)
{
+ bool is_secure = *is_secure_ptr;
+
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
- !regime_translation_disabled(env, ARMMMUIdx_Stage2, *is_secure)) {
- ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
- : ARMMMUIdx_Stage2;
+ !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) {
+ ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S
+ : ARMMMUIdx_Stage2;
GetPhysAddrResult s2 = {};
int ret;
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
- *is_secure, false, &s2, fi);
+ is_secure, false, &s2, fi);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
fi->stage2 = true;
fi->s1ptw = true;
- fi->s1ns = !*is_secure;
+ fi->s1ns = !is_secure;
return ~0;
}
if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
@@ -237,19 +239,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
fi->s2addr = addr;
fi->stage2 = true;
fi->s1ptw = true;
- fi->s1ns = !*is_secure;
+ fi->s1ns = !is_secure;
return ~0;
}
if (arm_is_secure_below_el3(env)) {
/* Check if page table walk is to secure or non-secure PA space. */
- if (*is_secure) {
- *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
+ if (is_secure) {
+ is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
} else {
- *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
+ is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
}
+ *is_secure_ptr = is_secure;
} else {
- assert(!*is_secure);
+ assert(!is_secure);
}
addr = s2.phys;
--
2.34.1
- [PATCH 27/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav5, (continued)
- [PATCH 27/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav5, Richard Henderson, 2022/07/03
- [PATCH 28/62] target/arm: Split out get_phys_addr_with_secure, Richard Henderson, 2022/07/03
- [PATCH 29/62] target/arm: Add is_secure parameter to v7m_read_half_insn, Richard Henderson, 2022/07/03
- [PATCH 30/62] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/07/03
- [PATCH 31/62] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/07/03
- [PATCH 32/62] target/arm: Add is_secure parameter to do_ats_write, Richard Henderson, 2022/07/03
- [PATCH 33/62] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/07/03
- [PATCH 34/62] target/arm: Reorg regime_translation_disabled, Richard Henderson, 2022/07/03
- [PATCH 35/62] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/07/03
- [PATCH 36/62] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/07/03
- [PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate,
Richard Henderson <=
- [PATCH 38/62] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/07/03
- [PATCH 39/62] target/arm: Remove env argument from combined_attrs_fwb, Richard Henderson, 2022/07/03
- [PATCH 40/62] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/07/03
- [PATCH 41/62] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/07/03
- [PATCH 42/62] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/07/03
- [PATCH 43/62] target/arm: Reorg get_phys_addr_disabled, Richard Henderson, 2022/07/03
- [PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS}, Richard Henderson, 2022/07/03
- [PATCH 45/62] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx, Richard Henderson, 2022/07/03
- [PATCH 46/62] target/arm: Use softmmu tlbs for page table walking, Richard Henderson, 2022/07/03
- [PATCH 47/62] target/arm: Hoist check for disabled stage2 translation., Richard Henderson, 2022/07/03