[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 09/27] aspeed: Add memory property to Aspeed SoC
From: |
Cédric Le Goater |
Subject: |
[PULL 09/27] aspeed: Add memory property to Aspeed SoC |
Date: |
Thu, 30 Jun 2022 13:23:53 +0200 |
From: Peter Delevoryas <pdel@fb.com>
Multi-SoC machines can use this property to specify a memory container
for each SoC. Single SoC machines will just specify get_system_memory().
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220624003701.1363500-3-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed.c | 4 ++++
hw/arm/aspeed_ast10x0.c | 5 ++---
hw/arm/aspeed_ast2600.c | 4 ++--
hw/arm/aspeed_soc.c | 12 +++++++-----
5 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index e8a104823d35..c8e903b821db 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -49,6 +49,7 @@ struct AspeedSoCState {
ARMCPU cpu[ASPEED_CPUS_NUM];
A15MPPrivState a7mpcore;
ARMv7MState armv7m;
+ MemoryRegion *memory;
MemoryRegion *dram_mr;
MemoryRegion dram_container;
MemoryRegion sram;
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index dc09773b0ba5..b43dc0fda853 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -329,6 +329,8 @@ static void aspeed_machine_init(MachineState *machine)
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
&error_abort);
+ object_property_set_link(OBJECT(&bmc->soc), "memory",
+ OBJECT(get_system_memory()), &error_abort);
object_property_set_link(OBJECT(&bmc->soc), "dram",
OBJECT(machine->ram), &error_abort);
if (machine->kernel_filename) {
@@ -1336,6 +1338,8 @@ static void aspeed_minibmc_machine_init(MachineState
*machine)
object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+ object_property_set_link(OBJECT(&bmc->soc), "memory",
+ OBJECT(get_system_memory()), &error_abort);
qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
amc->uart_default);
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 5df480a21f39..e074f80cc742 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -148,7 +148,6 @@ static void aspeed_soc_ast1030_realize(DeviceState
*dev_soc, Error **errp)
{
AspeedSoCState *s = ASPEED_SOC(dev_soc);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- MemoryRegion *system_memory = get_system_memory();
DeviceState *armv7m;
Error *err = NULL;
int i;
@@ -172,7 +171,7 @@ static void aspeed_soc_ast1030_realize(DeviceState
*dev_soc, Error **errp)
qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&s->armv7m), "memory",
- OBJECT(system_memory), &error_abort);
+ OBJECT(s->memory), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
/* Internal SRAM */
@@ -181,7 +180,7 @@ static void aspeed_soc_ast1030_realize(DeviceState
*dev_soc, Error **errp)
error_propagate(errp, err);
return;
}
- memory_region_add_subregion(system_memory,
+ memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM],
&s->sram);
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index a4d90daf3702..e4aa908faba6 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -291,7 +291,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev,
Error **errp)
object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
&error_abort);
object_property_set_link(OBJECT(&s->cpu[i]), "memory",
- OBJECT(get_system_memory()), &error_abort);
+ OBJECT(s->memory), &error_abort);
if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
return;
@@ -329,7 +329,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev,
Error **errp)
error_propagate(errp, err);
return;
}
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM], &s->sram);
/* DPMCU */
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index a53a0ca6d63a..502c23dd0218 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -243,7 +243,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
/* CPU */
for (i = 0; i < sc->num_cpus; i++) {
object_property_set_link(OBJECT(&s->cpu[i]), "memory",
- OBJECT(get_system_memory()), &error_abort);
+ OBJECT(s->memory), &error_abort);
if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
return;
}
@@ -256,7 +256,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
error_propagate(errp, err);
return;
}
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM], &s->sram);
/* SCU */
@@ -456,6 +456,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
}
static Property aspeed_soc_properties[] = {
+ DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default,
@@ -555,14 +557,14 @@ void aspeed_soc_uart_init(AspeedSoCState *s)
int i, uart;
/* Attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
+ serial_mm_init(s->memory, sc->memmap[s->uart_default], 2,
aspeed_soc_get_irq(s, s->uart_default), 38400,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
if (uart == s->uart_default) {
uart++;
}
- serial_mm_init(get_system_memory(), sc->memmap[uart], 2,
+ serial_mm_init(s->memory, sc->memmap[uart], 2,
aspeed_soc_get_irq(s, uart), 38400,
serial_hd(i), DEVICE_LITTLE_ENDIAN);
}
@@ -604,7 +606,7 @@ bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
}
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
return true;
}
--
2.35.3
- [PULL 00/27] aspeed queue, Cédric Le Goater, 2022/06/30
- [PULL 02/27] hw: m25p80: add tests for write protect (WP# and SRWD bit), Cédric Le Goater, 2022/06/30
- [PULL 03/27] aspeed: Set the dram container at the SoC level, Cédric Le Goater, 2022/06/30
- [PULL 01/27] hw: m25p80: add WP# pin and SRWD bit for write protection, Cédric Le Goater, 2022/06/30
- [PULL 04/27] aspeed/scu: Add trace events for read ops, Cédric Le Goater, 2022/06/30
- [PULL 07/27] aspeed/smc: Fix potential overflow, Cédric Le Goater, 2022/06/30
- [PULL 05/27] aspeed/i2c: Change trace event for NORMAL_STOP states, Cédric Le Goater, 2022/06/30
- [PULL 06/27] aspeed/hace: Accumulative mode supported, Cédric Le Goater, 2022/06/30
- [PULL 08/27] aspeed: Set CPU memory property explicitly, Cédric Le Goater, 2022/06/30
- [PULL 09/27] aspeed: Add memory property to Aspeed SoC,
Cédric Le Goater <=
- [PULL 10/27] aspeed: Remove usage of sysbus_mmio_map, Cédric Le Goater, 2022/06/30
- [PULL 12/27] aspeed: Remove use of qemu_get_cpu, Cédric Le Goater, 2022/06/30
- [PULL 11/27] aspeed: Map unimplemented devices in SoC memory, Cédric Le Goater, 2022/06/30
- [PULL 13/27] hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board, Cédric Le Goater, 2022/06/30
- [PULL 14/27] hw/arm/aspeed: add Qualcomm Firework BMC machine, Cédric Le Goater, 2022/06/30
- [PULL 15/27] hw/i2c: pmbus: Page #255 is valid page for read requests., Cédric Le Goater, 2022/06/30
- [PULL 17/27] hw/arm/aspeed: Add MAX31785 Fan controllers, Cédric Le Goater, 2022/06/30
- [PULL 16/27] hw/sensor: add Maxim MAX31785 device, Cédric Le Goater, 2022/06/30
- [PULL 18/27] hw/arm/aspeed: firework: Add Thermal Diodes, Cédric Le Goater, 2022/06/30
- [PULL 19/27] hw/arm/aspeed: firework: add I2C MUXes for VR channels, Cédric Le Goater, 2022/06/30