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Re: [PATCH v2 39/71] target/arm: Add SVL to TB flags
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v2 39/71] target/arm: Add SVL to TB flags |
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Date: |
Thu, 9 Jun 2022 16:33:39 +0100 |
On Tue, 7 Jun 2022 at 21:33, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We need SVL separate from VL for RDSVL at al, as well as
> ZA storage loads and stores, which do not require PSTATE.SM.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v2 30/71] target/arm: Implement SMSTART, SMSTOP, (continued)
- [PATCH v2 30/71] target/arm: Implement SMSTART, SMSTOP, Richard Henderson, 2022/06/07
- [PATCH v2 34/71] target/arm: Generalize cpu_arm_{get, set}_default_vec_len, Richard Henderson, 2022/06/07
- [PATCH v2 35/71] target/arm: Move arm_cpu_*_finalize to internals.h, Richard Henderson, 2022/06/07
- [PATCH v2 36/71] target/arm: Unexport aarch64_add_*_properties, Richard Henderson, 2022/06/07
- [PATCH v2 38/71] target/arm: Introduce sve_vqm1_for_el_sm, Richard Henderson, 2022/06/07
- [PATCH v2 39/71] target/arm: Add SVL to TB flags, Richard Henderson, 2022/06/07
- Re: [PATCH v2 39/71] target/arm: Add SVL to TB flags,
Peter Maydell <=
- [PATCH v2 32/71] target/arm: Create ARMVQMap, Richard Henderson, 2022/06/07
- [PATCH v2 37/71] target/arm: Add cpu properties for SME, Richard Henderson, 2022/06/07
- [PATCH v2 40/71] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h, Richard Henderson, 2022/06/07
- [PATCH v2 41/71] target/arm: Add infrastructure for disas_sme, Richard Henderson, 2022/06/07