Re: [PATCH v5 02/24] target/arm: Drop EL3 no EL2 fallbacks

[Peter Maydell]

On Thu, 5 May 2022 at 20:15, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo,
> and the local vpidr_regs definition, and rely on the
> squasing to ARM_CP_CONST while registering.

"squashing"

This patch is a behaviour change, which I think is correct, but
it could do with being called out more clearly in the commit
message. Specifically, for v7 with EL3 but not EL2, we used to
register RAZ/WI versions of all the registers in el3_no_el2_cp_reginfo[].
After this change we won't, because we only register el2_cp_reginfo
on v8 no-EL2 CPUs. As it happens, this is correct, because
(as described in the v7A/v7R Arm ARM DDI0406C.d section B3.15.3)
v7 treats these as "PL2-mode system control registers" which are
not supposed to be implemented if the Virtualization Extensions
are not implemented. (There is a weird special case for CNTVOFF,
but luckily it boils down to "it's OK to just UNDEF it".) But
it is a change from what we previously did.

This would be a migration compat break except that we've had
a bug for years that we haven't got round to fixing where migration
of 32-bit CPUs with EL3 implemented doesn't work...

With an improved commit message:
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM