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Re: [PATCH 0/5] target/arm: Support variable sized coprocessor registers
From: |
Peter Maydell |
Subject: |
Re: [PATCH 0/5] target/arm: Support variable sized coprocessor registers |
Date: |
Mon, 11 Apr 2022 10:22:59 +0100 |
On Mon, 11 Apr 2022 at 07:59, Gavin Shan <gshan@redhat.com> wrote:
>
> There are two arrays for each CPU, to store the indexes and values of the
> coprocessor registers. Currently, 8 bytes fixed storage space is reserved
> for each coprocessor register. However, larger coprocessor registers have
> been defined and exposed by KVM. Except SVE registers, no coprocessor
> register exceeds 8 bytes in size. It doesn't mean large coprocessor registers
> won't be exploited in future. For example, I'm looking into SDEI
> virtualization
> support, which isn't merged into Linux upstream yet. I have plan to add
> several coprocessor ("firmware pseudo") registers to assist the migration.
So, can you give an example of coprocessor registers which are
not 8 bytes in size? How are they accessed by the guest?
If we need to support them then we need to support them, but this
cover letter/series doesn't seem to me to provide enough detail
to make the case that they really are necessary.
Also, we support SVE today, and we don't have variable size
coprocessor registers. Is there a bug here that we would be
fixing ?
thanks
-- PMM
- [PATCH 0/5] target/arm: Support variable sized coprocessor registers, Gavin Shan, 2022/04/11
- [PATCH 1/5] target/arm/tcg: Indirect addressing for coprocessor register storage, Gavin Shan, 2022/04/11
- [PATCH 2/5] target/arm/hvf: Indirect addressing for coprocessor register storage, Gavin Shan, 2022/04/11
- [PATCH 3/5] target/arm/kvm: Indirect addressing for coprocessor register storage, Gavin Shan, 2022/04/11
- [PATCH 4/5] target/arm: Migrate coprocessor register indirect addressing information, Gavin Shan, 2022/04/11
- [PATCH 5/5] target/arm/kvm: Support coprocessor register with variable size, Gavin Shan, 2022/04/11
- Re: [PATCH 0/5] target/arm: Support variable sized coprocessor registers,
Peter Maydell <=
- Re: [PATCH 0/5] target/arm: Support variable sized coprocessor registers, Andrew Jones, 2022/04/11
- Re: [PATCH 0/5] target/arm: Support variable sized coprocessor registers, Gavin Shan, 2022/04/11