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[PATCH 0/5] target/arm: Support variable sized coprocessor registers
From: |
Gavin Shan |
Subject: |
[PATCH 0/5] target/arm: Support variable sized coprocessor registers |
Date: |
Mon, 11 Apr 2022 14:58:37 +0800 |
There are two arrays for each CPU, to store the indexes and values of the
coprocessor registers. Currently, 8 bytes fixed storage space is reserved
for each coprocessor register. However, larger coprocessor registers have
been defined and exposed by KVM. Except SVE registers, no coprocessor
register exceeds 8 bytes in size. It doesn't mean large coprocessor registers
won't be exploited in future. For example, I'm looking into SDEI virtualization
support, which isn't merged into Linux upstream yet. I have plan to add
several coprocessor ("firmware pseudo") registers to assist the migration.
This series adds one more array, to track the position or location in the
storage array (@cpreg_values) for the corresponding coprocessor register.
The storage space for one particular coprocessor register is always to
8 bytes so that we needn't worry about the alignment issue. In this way,
the coprocessor register size can be variable.
I had some internal discussion with Eric and Drew. They suggested to
send one mail to qemu-arm@nongnu.org, asking if there is any challenges
to support variable sized coprocessor registers. So another intention
of this series is to invoke the discussion.
PATCH[1-3] adds one more array (@cpreg_value_indexes) to track the location
in the storage array (@cpreg_values) for coprocessor registers. The storage
space for one particular coprocessor register is determined by the additional
array, which is named as indirect addressing mode. Each coprocessor register
is still having 8 bytes fixed storage space, so that thd old mechanism
(direct addressing mode) and indirect address mode can co-exist, event in
migration circumstance. PATCH[4] migrates the additional array. PATCH[5]
initializes @cpreg_value_indexes for KVM.
Gavin Shan (5):
target/arm/tcg: Indirect addressing for coprocessor register storage
target/arm/hvf: Indirect addressing for coprocessor register storage
target/arm/kvm: Indirect addressing for coprocessor register storage
target/arm: Migrate coprocessor register indirect addressing
information
target/arm/kvm: Support coprocessor register with variable size
target/arm/cpu.h | 12 +++++--
target/arm/helper.c | 27 +++++++++-----
target/arm/hvf/hvf.c | 20 +++++++++--
target/arm/kvm.c | 85 ++++++++++++++++++++++++++++++++++++++------
target/arm/machine.c | 30 ++++++++++++----
5 files changed, 145 insertions(+), 29 deletions(-)
--
2.23.0
- [PATCH 0/5] target/arm: Support variable sized coprocessor registers,
Gavin Shan <=
- [PATCH 1/5] target/arm/tcg: Indirect addressing for coprocessor register storage, Gavin Shan, 2022/04/11
- [PATCH 2/5] target/arm/hvf: Indirect addressing for coprocessor register storage, Gavin Shan, 2022/04/11
- [PATCH 3/5] target/arm/kvm: Indirect addressing for coprocessor register storage, Gavin Shan, 2022/04/11
- [PATCH 4/5] target/arm: Migrate coprocessor register indirect addressing information, Gavin Shan, 2022/04/11
- [PATCH 5/5] target/arm/kvm: Support coprocessor register with variable size, Gavin Shan, 2022/04/11
- Re: [PATCH 0/5] target/arm: Support variable sized coprocessor registers, Peter Maydell, 2022/04/11
- Re: [PATCH 0/5] target/arm: Support variable sized coprocessor registers, Andrew Jones, 2022/04/11