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[RFC PATCH 16/18] hw/riscv: update remaining machines due to riscv_hart_
From: |
Damien Hedde |
Subject: |
[RFC PATCH 16/18] hw/riscv: update remaining machines due to riscv_hart_array update |
Date: |
Wed, 30 Mar 2022 14:56:37 +0200 |
virt & spike machines have multiple sockets (but they still put
all cpus in the same default cluster). For these 2 machines
we disable the clustering in the array in order to keep the
behavior.
opentitan, sifive_e and shakti_c, were using the default cluster
too. But we can use the embedded cluster as it is equivalent.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
---
hw/riscv/opentitan.c | 4 ++--
hw/riscv/shakti_c.c | 4 ++--
hw/riscv/sifive_e.c | 4 ++--
hw/riscv/spike.c | 5 +++--
hw/riscv/virt.c | 5 +++--
5 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 2eb7454d8a..4e90610f1d 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -132,10 +132,10 @@ static void lowrisc_ibex_soc_realize(DeviceState
*dev_soc, Error **errp)
object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
+ object_property_set_int(OBJECT(&s->cpus), "num-cpus", ms->smp.cpus,
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080,
&error_abort);
- riscv_hart_array_realize(&s->cpus, &error_abort);
+ qdev_realize(DEVICE(&s->cpus), NULL, &error_abort);
/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 93e0c8dd68..5158ea6e8b 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -108,7 +108,7 @@ static void shakti_c_soc_state_realize(DeviceState *dev,
Error **errp)
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
MemoryRegion *system_memory = get_system_memory();
- riscv_hart_array_realize(&sss->cpus, &error_abort);
+ qdev_realize(DEVICE(&sss->cpus), NULL, &error_abort);
sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
(char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0,
@@ -171,7 +171,7 @@ static void shakti_c_soc_instance_init(Object *obj)
*/
object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
- object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
+ object_property_set_int(OBJECT(&sss->cpus), "num-cpus", 1,
&error_abort);
}
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 25ba0a8c85..c1e67c0f78 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -179,7 +179,7 @@ static void sifive_e_soc_init(Object *obj)
SiFiveESoCState *s = RISCV_E_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
- object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
+ object_property_set_int(OBJECT(&s->cpus), "num-cpus", ms->smp.cpus,
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004,
&error_abort);
object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
@@ -195,7 +195,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error
**errp)
object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
&error_abort);
- riscv_hart_array_realize(&s->cpus, &error_abort);
+ qdev_realize(DEVICE(&s->cpus), NULL, &error_abort);
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index b75e3656e1..17bba3c7fa 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -228,9 +228,10 @@ static void spike_board_init(MachineState *machine)
machine->cpu_type, &error_abort);
object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
base_hartid, &error_abort);
- object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+ object_property_set_int(OBJECT(&s->soc[i]), "num-cpus",
hart_count, &error_abort);
- riscv_hart_array_realize(&s->soc[i], &error_abort);
+ cpus_disable_clustering(CPUS(&s->soc[i]));
+ qdev_realize(DEVICE(&s->soc[i]), NULL, &error_abort);
/* Core Local Interruptor (timer and IPI) for each socket */
riscv_aclint_swi_create(
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 12036aa95b..c51b124330 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1221,9 +1221,10 @@ static void virt_machine_init(MachineState *machine)
machine->cpu_type, &error_abort);
object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
base_hartid, &error_abort);
- object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+ object_property_set_int(OBJECT(&s->soc[i]), "num-cpus",
hart_count, &error_abort);
- riscv_hart_array_realize(&s->soc[i], &error_abort);
+ cpus_disable_clustering(CPUS(&s->soc[i]));
+ qdev_realize(DEVICE(&s->soc[i]), NULL, &error_abort);
if (!kvm_enabled()) {
if (s->have_aclint) {
--
2.35.1
- [RFC PATCH 04/18] hw/cpu/cluster: make _cpu-cluster_ a subclass of _cpus_, (continued)
- [RFC PATCH 04/18] hw/cpu/cluster: make _cpu-cluster_ a subclass of _cpus_, Damien Hedde, 2022/03/30
- [RFC PATCH 07/18] hw/cpu/cpus: add a common start-powered-off property, Damien Hedde, 2022/03/30
- [RFC PATCH 01/18] define MAX_CLUSTERS in cpu.h instead of cluster.h, Damien Hedde, 2022/03/30
- [RFC PATCH 08/18] hw/arm/arm_cpus: add arm_cpus device, Damien Hedde, 2022/03/30
- [RFC PATCH 05/18] gdbstub: deal with _cpus_ object instead of _cpu-cluster_, Damien Hedde, 2022/03/30
- [RFC PATCH 09/18] hw/arm/xlnx-zynqmp: convert cpu clusters to arm_cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 10/18] hw/riscv/riscv_hart: prepare transition to cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 11/18] hw/riscv: prepare riscv_hart transition to cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 13/18] hw/riscv/spike: prepare riscv_hart transition to cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 15/18] hw/riscv/sifive_uµchip_pfsoc: apply riscv_hart_array update, Damien Hedde, 2022/03/30
- [RFC PATCH 16/18] hw/riscv: update remaining machines due to riscv_hart_array update,
Damien Hedde <=
- [RFC PATCH 14/18] hw/riscv/riscv_hart: use cpus as base class, Damien Hedde, 2022/03/30
- [RFC PATCH 17/18] hw/riscv/riscv_hart: remove temporary features, Damien Hedde, 2022/03/30
- [RFC PATCH 18/18] add myself as reviewer of the newly added _cpus_, Damien Hedde, 2022/03/30
- [RFC PATCH 12/18] hw/riscv/virt: prepare riscv_hart transition to cpus, Damien Hedde, 2022/03/30