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[RFC PATCH 10/18] hw/riscv/riscv_hart: prepare transition to cpus
From: |
Damien Hedde |
Subject: |
[RFC PATCH 10/18] hw/riscv/riscv_hart: prepare transition to cpus |
Date: |
Wed, 30 Mar 2022 14:56:31 +0200 |
riscv_hart_array does not need to be a sysbus device: it does not
have any mmio or sysbus irq.
We want to make it inherit the new cpus class so we need
a few tweaks:
+ a temporary helper realize so we can switch from sysbus_realize to
qdev_realize (will be removed afer the transition is done).
+ a helper function to get an hart from the array (the current storage
array field will be removed).
+ a helper function to get the number of harts in an array (the current
field will be removed).
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
---
include/hw/riscv/riscv_hart.h | 19 +++++++++++++++++++
hw/riscv/riscv_hart.c | 5 +++++
2 files changed, 24 insertions(+)
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index bbc21cdc9a..71747bf37c 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -41,4 +41,23 @@ struct RISCVHartArrayState {
RISCVCPU *harts;
};
+/**
+ * riscv_array_get_hart:
+ */
+static inline RISCVCPU *riscv_array_get_hart(RISCVHartArrayState *harts, int i)
+{
+ return &harts->harts[i];
+}
+
+/**
+ * riscv_array_get_num_harts:
+ */
+static inline unsigned riscv_array_get_num_harts(RISCVHartArrayState *harts)
+{
+ return harts->num_harts;
+}
+
+/* Temporary function until we migrated the riscv hart array to simple device
*/
+void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp);
+
#endif
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 613ea2aaa0..780fd3a59a 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -27,6 +27,11 @@
#include "hw/qdev-properties.h"
#include "hw/riscv/riscv_hart.h"
+void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp)
+{
+ sysbus_realize(SYS_BUS_DEVICE(state), errp);
+}
+
static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
--
2.35.1
- [RFC PATCH 00/18] user-creatable cpu clusters, Damien Hedde, 2022/03/30
- [RFC PATCH 02/18] hw/cpu/cpus: introduce _cpus_ device, Damien Hedde, 2022/03/30
- [RFC PATCH 03/18] hw/cpu/cpus: prepare to handle cpu clusters, Damien Hedde, 2022/03/30
- [RFC PATCH 06/18] hw/cpu/cluster: remove cluster_id now that gdbstub is updated, Damien Hedde, 2022/03/30
- [RFC PATCH 04/18] hw/cpu/cluster: make _cpu-cluster_ a subclass of _cpus_, Damien Hedde, 2022/03/30
- [RFC PATCH 07/18] hw/cpu/cpus: add a common start-powered-off property, Damien Hedde, 2022/03/30
- [RFC PATCH 01/18] define MAX_CLUSTERS in cpu.h instead of cluster.h, Damien Hedde, 2022/03/30
- [RFC PATCH 08/18] hw/arm/arm_cpus: add arm_cpus device, Damien Hedde, 2022/03/30
- [RFC PATCH 05/18] gdbstub: deal with _cpus_ object instead of _cpu-cluster_, Damien Hedde, 2022/03/30
- [RFC PATCH 09/18] hw/arm/xlnx-zynqmp: convert cpu clusters to arm_cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 10/18] hw/riscv/riscv_hart: prepare transition to cpus,
Damien Hedde <=
- [RFC PATCH 11/18] hw/riscv: prepare riscv_hart transition to cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 13/18] hw/riscv/spike: prepare riscv_hart transition to cpus, Damien Hedde, 2022/03/30
- [RFC PATCH 15/18] hw/riscv/sifive_uµchip_pfsoc: apply riscv_hart_array update, Damien Hedde, 2022/03/30
- [RFC PATCH 16/18] hw/riscv: update remaining machines due to riscv_hart_array update, Damien Hedde, 2022/03/30
- [RFC PATCH 14/18] hw/riscv/riscv_hart: use cpus as base class, Damien Hedde, 2022/03/30
- [RFC PATCH 17/18] hw/riscv/riscv_hart: remove temporary features, Damien Hedde, 2022/03/30
- [RFC PATCH 18/18] add myself as reviewer of the newly added _cpus_, Damien Hedde, 2022/03/30
- [RFC PATCH 12/18] hw/riscv/virt: prepare riscv_hart transition to cpus, Damien Hedde, 2022/03/30