---
hw/misc/aspeed_scu.c | 63 ++++++++++++++++++++++++++++++++++++
include/hw/misc/aspeed_scu.h | 24 ++++++++++++++
2 files changed, 87 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 150567f98a..19b03471fc 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -235,6 +235,15 @@ static uint32_t
aspeed_2600_scu_get_apb_freq(AspeedSCUState *s)
/ asc->apb_divider;
}
+static uint32_t aspeed_1030_scu_get_apb_freq(AspeedSCUState *s)
+{
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
+ uint32_t hpll = asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]);
+
+ return hpll / (SCU_AST1030_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL4]) + 1)
+ / asc->apb_divider;
+}
+
static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
@@ -482,6 +491,8 @@ static uint32_t aspeed_silicon_revs[] = {
AST2600_A1_SILICON_REV,
AST2600_A2_SILICON_REV,
AST2600_A3_SILICON_REV,
+ AST1030_A0_SILICON_REV,
+ AST1030_A1_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t silicon_rev)
@@ -770,12 +781,64 @@ static const TypeInfo aspeed_2600_scu_info = {
.class_init = aspeed_2600_scu_class_init,
};
+static const uint32_t ast1030_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
+ [AST2600_SYS_RST_CTRL] = 0xFFC3FED8,
+ [AST2600_SYS_RST_CTRL2] = 0x09FFFFFC,
+ [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
+ [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
+ [AST2600_DEBUG_CTRL2] = 0x00000000,
+ [AST2600_HPLL_PARAM] = 0x10004077,
+ [AST2600_HPLL_EXT] = 0x00000031,
+ [AST2600_CLK_SEL4] = 0x43F90900,
+ [AST2600_CLK_SEL5] = 0x40000000,
+ [AST2600_CHIP_ID0] = 0xDEADBEEF,
+ [AST2600_CHIP_ID1] = 0x0BADCAFE,
+};
+
+static void aspeed_ast1030_scu_reset(DeviceState *dev)
+{
+ AspeedSCUState *s = ASPEED_SCU(dev);
+ AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+
+ memcpy(s->regs, asc->resets, asc->nr_regs * 4);
+
+ s->regs[AST2600_SILICON_REV] = AST1030_A1_SILICON_REV;
+ s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
+ s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
+ s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
+ s->regs[PROT_KEY] = s->hw_prot_key;
+}
+
+static void aspeed_1030_scu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
+
+ dc->desc = "ASPEED 1030 System Control Unit";
+ dc->reset = aspeed_ast1030_scu_reset;
+ asc->resets = ast1030_a1_resets;
+ asc->calc_hpll = aspeed_2600_scu_calc_hpll;
+ asc->get_apb = aspeed_1030_scu_get_apb_freq;
+ asc->apb_divider = 2;
+ asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
+ asc->clkin_25Mhz = true;
+ asc->ops = &aspeed_ast2600_scu_ops;
+}
+
+static const TypeInfo aspeed_1030_scu_info = {
+ .name = TYPE_ASPEED_1030_SCU,
+ .parent = TYPE_ASPEED_SCU,
+ .instance_size = sizeof(AspeedSCUState),
+ .class_init = aspeed_1030_scu_class_init,
+};
+
static void aspeed_scu_register_types(void)
{
type_register_static(&aspeed_scu_info);
type_register_static(&aspeed_2400_scu_info);
type_register_static(&aspeed_2500_scu_info);
type_register_static(&aspeed_2600_scu_info);
+ type_register_static(&aspeed_1030_scu_info);
}
type_init(aspeed_scu_register_types);
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index fdc721846c..d2c485c8f6 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -19,6 +19,7 @@ OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass,
ASPEED_SCU)
#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
+#define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
@@ -45,6 +46,8 @@ struct AspeedSCUState {
#define AST2600_A1_SILICON_REV 0x05010303U
#define AST2600_A2_SILICON_REV 0x05020303U
#define AST2600_A3_SILICON_REV 0x05030303U
+#define AST1030_A0_SILICON_REV 0x80000000U
+#define AST1030_A1_SILICON_REV 0x80010000U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
@@ -335,4 +338,25 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
#define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24)
#define SCU_AST2600_H_PLL_OFF (0x1 << 23)
+/* SCU310 Clock Selection Register Set 4 (for Aspeed AST1030 SOC)
+ *
+ * 31 I3C Clock Source selection
+ * 30:28 I3C clock divider selection
+ * 26:24 MAC AHB clock divider selection
+ * 22:20 RGMII 125MHz clock divider ration
+ * 19:16 RGMII 50MHz clock divider ration
+ * 15 LHCLK clock generation/output enable control
+ * 14:12 LHCLK divider selection
+ * 11:8 APB Bus PCLK divider selection
+ * 7 Select PECI clock source
+ * 6 Select UART debug port clock source
+ * 5 Select UART6 clock source
+ * 4 Select UART5 clock source
+ * 3 Select UART4 clock source
+ * 2 Select UART3 clock source
+ * 1 Select UART2 clock source
+ * 0 Select UART1 clock source
+ */
+#define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf)
+
#endif /* ASPEED_SCU_H */