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Re: [PATCH for-6.2 12/34] target/arm: Implement MVE incrementing/decreme
From: |
Peter Maydell |
Subject: |
Re: [PATCH for-6.2 12/34] target/arm: Implement MVE incrementing/decrementing dup insns |
Date: |
Mon, 19 Jul 2021 15:25:11 +0100 |
On Fri, 16 Jul 2021 at 20:57, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/13/21 6:37 AM, Peter Maydell wrote:
> > +#define DO_VIDUP(OP, ESIZE, TYPE, FN) \
> > + uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \
> > + uint32_t offset, uint32_t imm) \
> > + { \
> > + TYPE *d = vd; \
> > + uint16_t mask = mve_element_mask(env); \
> > + unsigned e; \
> > + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
> > + mergemask(&d[H##ESIZE(e)], offset, mask); \
> > + offset = FN(offset, imm); \
> > + } \
> > + mve_advance_vpt(env); \
> > + return offset; \
> > + }
> > +
> > +#define DO_VIWDUP(OP, ESIZE, TYPE, FN) \
> > + uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \
> > + uint32_t offset, uint32_t wrap, \
> > + uint32_t imm) \
> > + { \
> > + TYPE *d = vd; \
> > + uint16_t mask = mve_element_mask(env); \
> > + unsigned e; \
> > + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
> > + mergemask(&d[H##ESIZE(e)], offset, mask); \
> > + offset = FN(offset, wrap, imm); \
> > + } \
> > + mve_advance_vpt(env); \
> > + return offset; \
> > + }
> > +
> > +#define DO_VIDUP_ALL(OP, FN) \
> > + DO_VIDUP(OP##b, 1, int8_t, FN) \
> > + DO_VIDUP(OP##h, 2, int16_t, FN) \
> > + DO_VIDUP(OP##w, 4, int32_t, FN)
> > +
> > +#define DO_VIWDUP_ALL(OP, FN) \
> > + DO_VIWDUP(OP##b, 1, int8_t, FN) \
> > + DO_VIWDUP(OP##h, 2, int16_t, FN) \
> > + DO_VIWDUP(OP##w, 4, int32_t, FN)
>
> Would it be useful to merge VIDUP and VIWDUP by passing wrap == 0?
> Or merging VIDUP and VDDUP by negating imm?
I think keeping the wrap-versions separate is clearer, but yes,
we might as well do the negate in the caller for VDDUP.
(VIWDUP and VDWDUP have different enough wrapping behaviour
that I'd prefer to not combine those).
thanks
-- PMM
- Re: [PATCH for-6.2 08/34] target/arm: Fix VPT advance when ECI is non-zero, (continued)
- [PATCH for-6.2 13/34] target/arm: Factor out gen_vpst(), Peter Maydell, 2021/07/13
- [PATCH for-6.2 10/34] target/arm: Fix VLDRB/H/W for predicated elements, Peter Maydell, 2021/07/13
- [PATCH for-6.2 11/34] target/arm: Implement MVE VMULL (polynomial), Peter Maydell, 2021/07/13
- [PATCH for-6.2 12/34] target/arm: Implement MVE incrementing/decrementing dup insns, Peter Maydell, 2021/07/13
- [PATCH for-6.2 15/34] target/arm: Implement MVE integer vector-vs-scalar comparisons, Peter Maydell, 2021/07/13
- [PATCH for-6.2 19/34] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats, Peter Maydell, 2021/07/13
- [PATCH for-6.2 17/34] target/arm: Implement MVE VMLAS, Peter Maydell, 2021/07/13
[PATCH for-6.2 18/34] target/arm: Implement MVE shift-by-scalar, Peter Maydell, 2021/07/13