[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v3 03/44] target/arm: Implement MVE VCLZ
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 03/44] target/arm: Implement MVE VCLZ |
Date: |
Mon, 21 Jun 2021 17:12:11 +0100 |
On Thu, 17 Jun 2021 at 13:16, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Implement the MVE VCLZ insn (and the necessary machinery
> for MVE 1-input vector ops).
>
> Note that for non-load instructions predication is always performed
> at a byte level granularity regardless of element size (R_ZLSJ),
> and so the masking logic here differs from that used in the VLDR
> and VSTR helpers.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This is the necessary fixup to deal with QEMU_GENERIC having
gone away in current master:
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 91a9366e281..f2fae523e24 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -185,7 +185,7 @@ DO_VSTR(vstrh_w, 2, stw, 4, int32_t)
/*
* The mergemask(D, R, M) macro performs the operation "*D = R" but
* storing only the bytes which correspond to 1 bits in M,
- * leaving other bytes in *D unchanged. We use QEMU_GENERIC
+ * leaving other bytes in *D unchanged. We use _Generic
* to select the correct implementation based on the type of D.
*/
@@ -234,30 +234,16 @@ static void mergemask_sq(int64_t *d, int64_t r,
uint16_t mask)
mergemask_uq((uint64_t *)d, r, mask);
}
-/*
- * mergemask() should never be passed an unknown type; catch this bug
- * at compile time with a link error if we can, otherwise at runtime.
- */
-#if defined(__OPTIMIZE__) && !defined(__SANITIZE_ADDRESS__)
-void unknown_mergemask_type(void *d, uint64_t r, uint16_t mask);
-#else
-static inline void unknown_mergemask_type(void *d, uint64_t r, uint16_t mask)
-{
- abort();
-}
-#endif
-
#define mergemask(D, R, M) \
- QEMU_GENERIC(D, \
- (uint8_t *, mergemask_ub), \
- (int8_t *, mergemask_sb), \
- (uint16_t *, mergemask_uh), \
- (int16_t *, mergemask_sh), \
- (uint32_t *, mergemask_uw), \
- (int32_t *, mergemask_sw), \
- (uint64_t *, mergemask_uq), \
- (int64_t *, mergemask_sq), \
- unknown_mergemask_type)(D, R, M)
+ _Generic(D, \
+ uint8_t *: mergemask_ub, \
+ int8_t *: mergemask_sb, \
+ uint16_t *: mergemask_uh, \
+ int16_t *: mergemask_sh, \
+ uint32_t *: mergemask_uw, \
+ int32_t *: mergemask_sw, \
+ uint64_t *: mergemask_uq, \
+ int64_t *: mergemask_sq)(D, R, M)
#define DO_1OP(OP, ESIZE, TYPE, FN) \
void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
thanks
-- PMM
- [PATCH v3 00/44] target/arm: First slice of MVE implementation, Peter Maydell, 2021/06/17
- [PATCH v3 02/44] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/17
- [PATCH v3 01/44] target/arm: Implement MVE VLDR/VSTR (non-widening forms), Peter Maydell, 2021/06/17
- [PATCH v3 03/44] target/arm: Implement MVE VCLZ, Peter Maydell, 2021/06/17
- [PATCH v3 04/44] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/17
- [PATCH v3 06/44] target/arm: Implement MVE VMVN (register), Peter Maydell, 2021/06/17
- [PATCH v3 05/44] target/arm: Implement MVE VREV16, VREV32, VREV64, Peter Maydell, 2021/06/17
- [PATCH v3 09/44] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, Peter Maydell, 2021/06/17
- [PATCH v3 08/44] target/arm: Implement MVE VNEG, Peter Maydell, 2021/06/17
- [PATCH v3 07/44] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/17
- [PATCH v3 12/44] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/17
- [PATCH v3 11/44] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/17
- [PATCH v3 10/44] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/17
- [PATCH v3 14/44] target/arm: Implement MVE VRMULH, Peter Maydell, 2021/06/17