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Re: [PATCH v1 07/11] target/arm: Implement bfloat16 dot product (indexed
From: |
Peter Maydell |
Subject: |
Re: [PATCH v1 07/11] target/arm: Implement bfloat16 dot product (indexed) |
Date: |
Tue, 18 May 2021 13:24:57 +0100 |
On Sat, 17 Apr 2021 at 01:06, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This is BFDOT for both AArch64 AdvSIMD and SVE,
> and VDOT.BF16 for AArch32 NEON.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.h | 2 ++
> target/arm/neon-shared.decode | 2 ++
> target/arm/sve.decode | 3 +++
> target/arm/translate-a64.c | 41 +++++++++++++++++++++++++--------
> target/arm/translate-sve.c | 12 ++++++++++
> target/arm/vec_helper.c | 20 ++++++++++++++++
> target/arm/translate-neon.c.inc | 9 ++++++++
> 7 files changed, 80 insertions(+), 9 deletions(-)
>
> @@ -13578,13 +13592,22 @@ static void disas_simd_indexed(DisasContext *s,
> uint32_t insn)
> u ? gen_helper_gvec_udot_idx_b
> : gen_helper_gvec_sdot_idx_b);
> return;
> - case 0x0f: /* SUDOT, USDOT */
> - gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
> - extract32(insn, 23, 1)
> - ? gen_helper_gvec_usdot_idx_b
> - : gen_helper_gvec_sudot_idx_b);
> - return;
> -
> + case 0x0f:
> + switch (extract32(insn, 22, 2)) {
You already have bits [23:22] in 'size' at this point, I think.
> + case 0: /* SUDOT */
> + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
> + gen_helper_gvec_sudot_idx_b);
> + return;
> + case 1: /* BFDOT */
> + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
> + gen_helper_gvec_bfdot_idx);
> + return;
> + case 2: /* USDOT */
> + gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
> + gen_helper_gvec_usdot_idx_b);
> + return;
> + }
> + g_assert_not_reached();
otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH v1 07/11] target/arm: Implement bfloat16 dot product (indexed),
Peter Maydell <=