Re: [PATCH v1 06/11] target/arm: Implement bfloat16 dot product (vector)

[Peter Maydell]

On Sat, 17 Apr 2021 at 01:02, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This is BFDOT for both AArch64 AdvSIMD and SVE,
> and VDOT.BF16 for AArch32 NEON.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> @@ -12326,6 +12336,16 @@ static void 
> disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
>          }
>          return;
>
> +    case 0xf: /* BFDOT */
> +        switch (size) {
> +        case 1:
> +            gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, 
> gen_helper_gvec_bfdot);
> +            break;
> +        default:
> +            g_assert_not_reached();
> +        }
> +        return;

The switch on size here seems unnecessary to me given we've already
decoded size earlier in the function.

> +
>      default:
>          g_assert_not_reached();
>      }
> diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
> index 8cc53892d6..aed8a565e0 100644
> --- a/target/arm/translate-neon.c.inc
> +++ b/target/arm/translate-neon.c.inc
> @@ -287,6 +287,15 @@ static bool trans_VUSDOT(DisasContext *s, arg_VUSDOT *a)
>                          gen_helper_gvec_usdot_b);
>  }
>
> +static bool trans_VDOT_b16(DisasContext *s, arg_VDOT_b16 *a)
> +{
> +    if (!dc_isar_feature(aa32_bf16, s)) {
> +        return false;
> +    }

Again, not sure if we need a FEATURE_NEON check ?


> +    return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0,
> +                        gen_helper_gvec_bfdot);
> +}
> +
>  static bool trans_VFML(DisasContext *s, arg_VFML *a)
>  {
>      int opr_sz;

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM