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[PATCH v4 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (
From: |
Richard Henderson |
Subject: |
[PATCH v4 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) |
Date: |
Fri, 16 Apr 2021 11:59:57 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d3bda16ecd..2a82dbbd6d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3635,7 +3635,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
bool is_postidx = extract32(insn, 23, 1);
bool is_q = extract32(insn, 30, 1);
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
- MemOp endian = s->be_data;
+ MemOp endian, align, mop;
int total; /* total bytes */
int elements; /* elements per vector */
@@ -3703,6 +3703,7 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
}
/* For our purposes, bytes are always little-endian. */
+ endian = s->be_data;
if (size == 0) {
endian = MO_LE;
}
@@ -3721,11 +3722,17 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
* Consecutive little-endian elements from a single register
* can be promoted to a larger little-endian operation.
*/
+ align = MO_ALIGN;
if (selem == 1 && endian == MO_LE) {
+ align = pow2_align(size);
size = 3;
}
- elements = (is_q ? 16 : 8) >> size;
+ if (!s->align_mem) {
+ align = 0;
+ }
+ mop = endian | size | align;
+ elements = (is_q ? 16 : 8) >> size;
tcg_ebytes = tcg_const_i64(1 << size);
for (r = 0; r < rpt; r++) {
int e;
@@ -3734,9 +3741,9 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
for (xs = 0; xs < selem; xs++) {
int tt = (rt + r + xs) % 32;
if (is_store) {
- do_vec_st(s, tt, e, clean_addr, size | endian);
+ do_vec_st(s, tt, e, clean_addr, mop);
} else {
- do_vec_ld(s, tt, e, clean_addr, size | endian);
+ do_vec_ld(s, tt, e, clean_addr, mop);
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
}
--
2.25.1
- [PATCH v4 23/30] target/arm: Enforce alignment for VLDn/VSTn (single), (continued)
- [PATCH v4 23/30] target/arm: Enforce alignment for VLDn/VSTn (single), Richard Henderson, 2021/04/16
- [PATCH v4 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple), Richard Henderson, 2021/04/16
- [PATCH v4 25/30] target/arm: Use finalize_memop for aa64 fpr load/store, Richard Henderson, 2021/04/16
- [PATCH v4 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel, Richard Henderson, 2021/04/16
- [PATCH v4 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single), Richard Henderson, 2021/04/16
- [PATCH v4 24/30] target/arm: Use finalize_memop for aa64 gpr load/store, Richard Henderson, 2021/04/16
- [PATCH v4 21/30] target/arm: Enforce alignment for VLDn (all lanes), Richard Henderson, 2021/04/16
- [PATCH v4 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st, Richard Henderson, 2021/04/16
- [PATCH v4 30/30] target/arm: Enforce alignment for sve LD1R, Richard Henderson, 2021/04/16
- [PATCH v4 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple),
Richard Henderson <=
- Re: [PATCH v4 for-6.1 00/39] target/arm: enforce alignment, Peter Maydell, 2021/04/16