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[PATCH v4 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (
From: |
Richard Henderson |
Subject: |
[PATCH v4 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single) |
Date: |
Fri, 16 Apr 2021 11:59:58 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2a82dbbd6d..95897e63af 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3815,6 +3815,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
int index = is_q << 3 | S << 2 | size;
int xs, total;
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
+ MemOp mop;
if (extract32(insn, 31, 1)) {
unallocated_encoding(s);
@@ -3876,6 +3877,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
total);
+ mop = finalize_memop(s, scale);
tcg_ebytes = tcg_const_i64(1 << scale);
for (xs = 0; xs < selem; xs++) {
@@ -3883,8 +3885,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
/* Load and replicate to all elements */
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr,
- get_mem_index(s), s->be_data + scale);
+ tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop);
tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
(is_q + 1) * 8, vec_full_reg_size(s),
tcg_tmp);
@@ -3892,9 +3893,9 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
} else {
/* Load/store one element per register */
if (is_load) {
- do_vec_ld(s, rt, index, clean_addr, scale | s->be_data);
+ do_vec_ld(s, rt, index, clean_addr, mop);
} else {
- do_vec_st(s, rt, index, clean_addr, scale | s->be_data);
+ do_vec_st(s, rt, index, clean_addr, mop);
}
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
--
2.25.1
- [PATCH v4 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, (continued)
- [PATCH v4 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Richard Henderson, 2021/04/16
- [PATCH v4 17/30] target/arm: Enforce alignment for RFE, Richard Henderson, 2021/04/16
- [PATCH v4 19/30] target/arm: Enforce alignment for VLDM/VSTM, Richard Henderson, 2021/04/16
- [PATCH v4 16/30] target/arm: Enforce alignment for LDM/STM, Richard Henderson, 2021/04/16
- [PATCH v4 20/30] target/arm: Enforce alignment for VLDR/VSTR, Richard Henderson, 2021/04/16
- [PATCH v4 18/30] target/arm: Enforce alignment for SRS, Richard Henderson, 2021/04/16
- [PATCH v4 23/30] target/arm: Enforce alignment for VLDn/VSTn (single), Richard Henderson, 2021/04/16
- [PATCH v4 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple), Richard Henderson, 2021/04/16
- [PATCH v4 25/30] target/arm: Use finalize_memop for aa64 fpr load/store, Richard Henderson, 2021/04/16
- [PATCH v4 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel, Richard Henderson, 2021/04/16
- [PATCH v4 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single),
Richard Henderson <=
- [PATCH v4 24/30] target/arm: Use finalize_memop for aa64 gpr load/store, Richard Henderson, 2021/04/16
- [PATCH v4 21/30] target/arm: Enforce alignment for VLDn (all lanes), Richard Henderson, 2021/04/16
- [PATCH v4 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st, Richard Henderson, 2021/04/16
- [PATCH v4 30/30] target/arm: Enforce alignment for sve LD1R, Richard Henderson, 2021/04/16
- [PATCH v4 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple), Richard Henderson, 2021/04/16
- Re: [PATCH v4 for-6.1 00/39] target/arm: enforce alignment, Peter Maydell, 2021/04/16