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[PATCH 09/15] target/arm: Implement VLDR/VSTR system register
From: |
Peter Maydell |
Subject: |
[PATCH 09/15] target/arm: Implement VLDR/VSTR system register |
Date: |
Mon, 16 Nov 2020 16:08:25 +0000 |
Implement the new-in-v8.1M VLDR/VSTR variants which directly
read or write FP system registers to memory.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/vfp.decode | 14 ++++++
target/arm/translate-vfp.c.inc | 89 ++++++++++++++++++++++++++++++++++
2 files changed, 103 insertions(+)
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 51f143b4a51..45e3023840b 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -84,6 +84,20 @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8
vd=%vd_sp
VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
+# M-profile VLDR/VSTR to sysreg
+%vldr_sysreg 22:1 13:3
+%imm7_0x4 0:7 !function=times_4
+
+&vldr_sysreg rn reg imm a w p
+@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \
+ reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg
+
+# P=0 W=0 is SEE "Related encodings", so split into two patterns
+VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1
+VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0
w=1
+VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1
+VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0
w=1
+
# We split the load/store multiple up into two patterns to avoid
# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
# grouping:
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 5d880d12116..cc115f1d35d 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -912,6 +912,95 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS
*a)
return true;
}
+static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value)
+{
+ arg_vldr_sysreg *a = opaque;
+ uint32_t offset = a->imm;
+ TCGv_i32 addr;
+
+ if (!a->a) {
+ offset = - offset;
+ }
+
+ addr = load_reg(s, a->rn);
+ if (a->p) {
+ tcg_gen_addi_i32(addr, addr, offset);
+ }
+
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+ gen_helper_v8m_stackcheck(cpu_env, addr);
+ }
+
+ gen_aa32_st32(s, value, addr, get_mem_index(s));
+ tcg_temp_free_i32(value);
+
+ if (a->w) {
+ /* writeback */
+ if (!a->p) {
+ tcg_gen_addi_i32(addr, addr, offset);
+ }
+ store_reg(s, a->rn, addr);
+ } else {
+ tcg_temp_free_i32(addr);
+ }
+}
+
+static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque)
+{
+ arg_vldr_sysreg *a = opaque;
+ uint32_t offset = a->imm;
+ TCGv_i32 addr;
+ TCGv_i32 value = tcg_temp_new_i32();
+
+ if (!a->a) {
+ offset = - offset;
+ }
+
+ addr = load_reg(s, a->rn);
+ if (a->p) {
+ tcg_gen_addi_i32(addr, addr, offset);
+ }
+
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+ gen_helper_v8m_stackcheck(cpu_env, addr);
+ }
+
+ gen_aa32_ld32u(s, value, addr, get_mem_index(s));
+
+ if (a->w) {
+ /* writeback */
+ if (!a->p) {
+ tcg_gen_addi_i32(addr, addr, offset);
+ }
+ store_reg(s, a->rn, addr);
+ } else {
+ tcg_temp_free_i32(addr);
+ }
+ return value;
+}
+
+static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+ return false;
+ }
+ if (a->rn == 15) {
+ return false;
+ }
+ return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a);
+}
+
+static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
+{
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+ return false;
+ }
+ if (a->rn == 15) {
+ return false;
+ }
+ return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a);
+}
+
static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
{
TCGv_i32 tmp;
--
2.20.1
- [PATCH 03/15] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, (continued)
- [PATCH 03/15] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, Peter Maydell, 2020/11/16
- [PATCH 06/15] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/11/16
- [PATCH 04/15] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/11/16
- [PATCH 07/15] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/11/16
- [PATCH 08/15] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/11/16
- [PATCH 09/15] target/arm: Implement VLDR/VSTR system register,
Peter Maydell <=
- [PATCH 10/15] target/arm: Implement M-profile FPSCR_nzcvqc, Peter Maydell, 2020/11/16
- [PATCH 11/15] target/arm: Use new FPCR_NZCV_MASK constant, Peter Maydell, 2020/11/16
- [PATCH 12/15] target/arm: Factor out preserve-fp-state from full_vfp_access_check(), Peter Maydell, 2020/11/16
- [PATCH 13/15] target/arm: Implement FPCXT_S fp system register, Peter Maydell, 2020/11/16
- [PATCH 15/15] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M, Peter Maydell, 2020/11/16
- [PATCH 14/15] target/arm: Implement FPCXT_NS fp system register, Peter Maydell, 2020/11/16