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[PATCH 05/15] target/arm: Implement CLRM instruction
From: |
Peter Maydell |
Subject: |
[PATCH 05/15] target/arm: Implement CLRM instruction |
Date: |
Mon, 16 Nov 2020 16:08:21 +0000 |
In v8.1M the new CLRM instruction allows zeroing an arbitrary set of
the general-purpose registers and APSR. Implement this.
The encoding is a subset of the LDMIA T2 encoding, using what would
be Rn=0b1111 (which UNDEFs for LDMIA).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/t32.decode | 6 +++++-
target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 8152739b52b..59ab974c661 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -609,7 +609,11 @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. ....
@rrr_rot
STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0
STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1
-LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
+{
+ # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding
+ CLRM 1110 1000 1001 1111 list:16
+ LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
+}
LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1
&rfe !extern rn w pu
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4b17b2e0d46..ac8c118427f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7965,6 +7965,44 @@ static bool trans_LDM_t16(DisasContext *s,
arg_ldst_block *a)
return do_ldm(s, a, 1);
}
+static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
+{
+ int i;
+ TCGv_i32 zero;
+
+ if (!dc_isar_feature(aa32_m_sec_state, s)) {
+ return false;
+ }
+
+ if (extract32(a->list, 13, 1)) {
+ return false;
+ }
+
+ if (!a->list) {
+ /* UNPREDICTABLE; we choose to UNDEF */
+ return false;
+ }
+
+ zero = tcg_const_i32(0);
+ for (i = 0; i < 15; i++) {
+ if (extract32(a->list, i, 1)) {
+ /* Clear R[i] */
+ tcg_gen_mov_i32(cpu_R[i], zero);
+ }
+ }
+ if (extract32(a->list, 15, 1)) {
+ /*
+ * Clear APSR (by calling the MSR helper with the same argument
+ * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
+ */
+ TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
+ gen_helper_v7m_msr(cpu_env, maskreg, zero);
+ tcg_temp_free_i32(maskreg);
+ }
+ tcg_temp_free_i32(zero);
+ return true;
+}
+
/*
* Branch, branch with link
*/
--
2.20.1
- [PATCH 00/15] target/arm: More v8.1M features, Peter Maydell, 2020/11/16
- [PATCH 01/15] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault, Peter Maydell, 2020/11/16
- [PATCH 02/15] target/arm: Implement v8.1M PXN extension, Peter Maydell, 2020/11/16
- [PATCH 05/15] target/arm: Implement CLRM instruction,
Peter Maydell <=
- [PATCH 03/15] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, Peter Maydell, 2020/11/16
- [PATCH 06/15] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/11/16
- [PATCH 04/15] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/11/16
- [PATCH 07/15] target/arm: Refactor M-profile VMSR/VMRS handling, Peter Maydell, 2020/11/16
- [PATCH 08/15] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/11/16