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Re: [PATCH 6/6] hw/gpio: Add GPIO model for Nuvoton NPCM7xx
From: |
Peter Maydell |
Subject: |
Re: [PATCH 6/6] hw/gpio: Add GPIO model for Nuvoton NPCM7xx |
Date: |
Tue, 20 Oct 2020 14:07:28 +0100 |
On Fri, 9 Oct 2020 at 00:22, Havard Skinnemoen <hskinnemoen@google.com> wrote:
>
> The NPCM7xx chips have multiple GPIO controllers that are mostly
> identical except for some minor differences like the reset values of
> some registers. Each controller controls up to 32 pins.
>
> Each individual pin is modeled as a pair of unnamed GPIOs -- one for
> emitting the actual pin state, and one for driving the pin externally.
> Like the nRF51 GPIO controller, a gpio level may be negative, which
> means the pin is not driven, or floating.
>
> Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
> +static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data)
> +{
> + ResettableClass *reset = RESETTABLE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + QEMU_BUILD_BUG_ON(NPCM7XX_GPIO_REGS_END > NPCM7XX_GPIO_NR_REGS);
> +
> + dc->desc = "NPCM7xx GPIO Controller";
> + reset->phases.enter = npcm7xx_gpio_enter_reset;
> + reset->phases.hold = npcm7xx_gpio_hold_reset;
> + device_class_set_props(dc, npcm7xx_gpio_properties);
> +}
Missing vmstate struct. Otherwise device looks good.
thanks
-- PMM
- [PATCH 2/6] Move npcm7xx_timer_reached_zero call out of npcm7xx_timer_pause, (continued)
- [PATCH 2/6] Move npcm7xx_timer_reached_zero call out of npcm7xx_timer_pause, Havard Skinnemoen, 2020/10/08
- [PATCH 4/6] hw/misc: Add npcm7xx random number generator, Havard Skinnemoen, 2020/10/08
- [PATCH 5/6] hw/arm/npcm7xx: Add EHCI and OHCI controllers, Havard Skinnemoen, 2020/10/08
- [PATCH 3/6] hw/timer: Adding watchdog for NPCM7XX Timer., Havard Skinnemoen, 2020/10/08
- [PATCH 6/6] hw/gpio: Add GPIO model for Nuvoton NPCM7xx, Havard Skinnemoen, 2020/10/08
- Re: [PATCH 6/6] hw/gpio: Add GPIO model for Nuvoton NPCM7xx,
Peter Maydell <=
- Re: [PATCH 0/6] Additional NPCM7xx features, devices and tests, Peter Maydell, 2020/10/20