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Re: [PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile L
From: |
Richard Henderson |
Subject: |
Re: [PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension |
Date: |
Mon, 19 Oct 2020 09:00:39 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 10/19/20 8:13 AM, Peter Maydell wrote:
> If the M-profile low-overhead-branch extension is implemented, FPSCR
> bits [18:16] are a new field LTPSIZE. If MVE is not implemented
> (currently always true for us) then this field always reads as 4 and
> ignores writes.
>
> These bits used to be the vector-length field for the old
> short-vector extension, so we need to take care that they are not
> misinterpreted as setting vec_len. We do this with a rearrangement
> of the vfp_set_fpscr() code that deals with vec_len, vec_stride
> and also the QC bit; this obviates the need for the M-profile
> only masking step that we used to have at the start of the function.
>
> We provide a new field in CPUState for LTPSIZE, even though this
> will always be 4, in preparation for MVE, so we don't have to
> come back later and split it out of the vfp.xregs[FPSCR] value.
> (This state struct field will be saved and restored as part of
> the FPSCR value via the vmstate_fpscr in machine.c.)
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 1 +
> target/arm/cpu.c | 9 +++++++++
> target/arm/vfp_helper.c | 6 ++++++
> 3 files changed, 16 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- [PATCH v2 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, (continued)
- [PATCH v2 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/19
- [PATCH v2 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/19
- [PATCH v2 03/10] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/19
- [PATCH v2 05/10] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/19
- [PATCH v2 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/19
- [PATCH v2 09/10] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16, Peter Maydell, 2020/10/19
- [PATCH v2 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/19
- [PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, Peter Maydell, 2020/10/19
- Re: [PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension,
Richard Henderson <=