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[PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB e
From: |
Peter Maydell |
Subject: |
[PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension |
Date: |
Mon, 19 Oct 2020 16:13:01 +0100 |
If the M-profile low-overhead-branch extension is implemented, FPSCR
bits [18:16] are a new field LTPSIZE. If MVE is not implemented
(currently always true for us) then this field always reads as 4 and
ignores writes.
These bits used to be the vector-length field for the old
short-vector extension, so we need to take care that they are not
misinterpreted as setting vec_len. We do this with a rearrangement
of the vfp_set_fpscr() code that deals with vec_len, vec_stride
and also the QC bit; this obviates the need for the M-profile
only masking step that we used to have at the start of the function.
We provide a new field in CPUState for LTPSIZE, even though this
will always be 4, in preparation for MVE, so we don't have to
come back later and split it out of the vfp.xregs[FPSCR] value.
(This state struct field will be saved and restored as part of
the FPSCR value via the vmstate_fpscr in machine.c.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 1 +
target/arm/cpu.c | 9 +++++++++
target/arm/vfp_helper.c | 6 ++++++
3 files changed, 16 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a432f301f11..49cd5cabcf2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -549,6 +549,7 @@ typedef struct CPUARMState {
uint32_t fpdscr[M_REG_NUM_BANKS];
uint32_t cpacr[M_REG_NUM_BANKS];
uint32_t nsacr;
+ int ltpsize;
} v7m;
/* Information associated with an exception about to be taken:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 186ee621a65..07492e9f9a4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -255,6 +255,15 @@ static void arm_cpu_reset(DeviceState *dev)
uint8_t *rom;
uint32_t vecbase;
+ if (cpu_isar_feature(aa32_lob, cpu)) {
+ /*
+ * LTPSIZE is constant 4 if MVE not implemented, and resets
+ * to an UNKNOWN value if MVE is implemented. We choose to
+ * always reset to 4.
+ */
+ env->v7m.ltpsize = 4;
+ }
+
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
env->v7m.secure = true;
} else {
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index c3d01d781b6..bf608d7aef3 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -174,6 +174,12 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
| (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20);
+ /*
+ * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
+ * two is not applicable to this CPU will always be zero.
+ */
+ fpscr |= env->v7m.ltpsize << 16;
+
fpscr |= vfp_get_fpscr_from_host(env);
i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
--
2.20.1
- Re: [PATCH v2 02/10] target/arm: Implement v8.1M NOCP handling, (continued)
- [PATCH v2 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/19
- [PATCH v2 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/19
- [PATCH v2 03/10] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/19
- [PATCH v2 05/10] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/19
- [PATCH v2 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/19
- [PATCH v2 09/10] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16, Peter Maydell, 2020/10/19
- [PATCH v2 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/19
- [PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension,
Peter Maydell <=