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Re: [PATCH v7 13/42] target/arm: Define arm_cpu_do_unaligned_access for
From: |
Peter Maydell |
Subject: |
Re: [PATCH v7 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only |
Date: |
Thu, 18 Jun 2020 18:45:00 +0100 |
On Thu, 18 Jun 2020 at 18:04, Richard Henderson
<richard.henderson@linaro.org> wrote:
> First, this could definitely be delayed to the follow-on linux-user patch set.
>
> Second, in the linux-user patch set, I decode the syndrome data to determine
> what kind of segv to deliver for MTE synchronous faults. It would be easy to
> extend that just a little to notice the usual syndrome for unaligned accesses.
> Which may be less confusing than abusing the v7m exception code?
Yeah, if we're going to look at syndrome data anyway that might
be clearer.
The other thing that really it would be nice if we were able
to feed through (via syndrome info or otherwise) is the difference
between SIGSEGV with si_code == SEGV_ACCERR vs SEGV_MAPERR.
At the moment handle_cpu_signal() knows the difference, but it
doesn't have a way to pass this through to tlb_fill, and then
cpu_loop() has to make up a si_code when it gets the EXCP_DATA_ABORT.
I mention this mostly in case it affects how you want to design
how you treat alignment and MTE faults -- it might be that the
si_code stuff is better dealt with entirely differently.
thanks
-- PMM
[PATCH v7 12/42] target/arm: Implement the SUBP instruction, Richard Henderson, 2020/06/02
[PATCH v7 14/42] target/arm: Add helper_probe_access, Richard Henderson, 2020/06/02
[PATCH v7 16/42] target/arm: Implement the STGP instruction, Richard Henderson, 2020/06/02
[PATCH v7 15/42] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/06/02
[PATCH v7 17/42] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/06/02