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[PATCH v2 10/17] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG
From: |
Richard Henderson |
Subject: |
[PATCH v2 10/17] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG |
Date: |
Thu, 4 Jun 2020 21:17:26 -0700 |
These prctl fields are required for the function of MTE.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/target_syscall.h | 9 ++++++
linux-user/syscall.c | 46 +++++++++++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/linux-user/aarch64/target_syscall.h
b/linux-user/aarch64/target_syscall.h
index 5fb0bf4a5d..779ca0c805 100644
--- a/linux-user/aarch64/target_syscall.h
+++ b/linux-user/aarch64/target_syscall.h
@@ -32,5 +32,14 @@ struct target_pt_regs {
#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55
#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56
# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0)
+/* MTE tag check fault modes */
+# define TARGET_PR_MTE_TCF_SHIFT 1
+# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT)
+# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT)
+# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT)
+# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT)
+/* MTE tag inclusion mask */
+# define TARGET_PR_MTE_TAG_SHIFT 3
+# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT)
#endif /* AARCH64_TARGET_SYSCALL_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index e4da53c5b3..9cf3ce872d 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -10463,10 +10463,47 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
case TARGET_PR_SET_TAGGED_ADDR_CTRL:
{
abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE;
+ CPUARMState *env = cpu_env;
+ ARMCPU *cpu = env_archcpu(env);
+
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ valid_mask |= TARGET_PR_MTE_TCF_MASK;
+ valid_mask |= TARGET_PR_MTE_TAG_MASK;
+ }
if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) {
return -TARGET_EINVAL;
}
+
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ switch (arg2 & TARGET_PR_MTE_TCF_MASK) {
+ case TARGET_PR_MTE_TCF_NONE:
+ case TARGET_PR_MTE_TCF_SYNC:
+ case TARGET_PR_MTE_TCF_ASYNC:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
+ * Note that the syscall values are consistent with hw.
+ */
+ env->cp15.sctlr_el[1] =
+ deposit64(env->cp15.sctlr_el[1], 38, 2,
+ arg2 >> TARGET_PR_MTE_TCF_SHIFT);
+
+ /*
+ * Write PR_MTE_TAG to GCR_EL1[Exclude].
+ * Note that the syscall uses an include mask,
+ * and hardware uses an exclude mask -- invert.
+ */
+ env->cp15.gcr_el1 =
+ deposit64(env->cp15.gcr_el1, 0, 16,
+ ~arg2 >> TARGET_PR_MTE_TAG_SHIFT);
+ arm_rebuild_hflags(env);
+ }
+
untagged_addr_mask = (arg2 & TARGET_PR_TAGGED_ADDR_ENABLE
? MAKE_64BIT_MASK(0, 56) : -1);
return 0;
@@ -10474,6 +10511,8 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
case TARGET_PR_GET_TAGGED_ADDR_CTRL:
{
abi_long ret = 0;
+ CPUARMState *env = cpu_env;
+ ARMCPU *cpu = env_archcpu(env);
if (arg2 || arg3 || arg4 || arg5) {
return -TARGET_EINVAL;
@@ -10481,6 +10520,13 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
if (~untagged_addr_mask != 0) {
ret |= TARGET_PR_TAGGED_ADDR_ENABLE;
}
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ /* See above. */
+ ret |= (extract64(env->cp15.sctlr_el[1], 38, 2)
+ << TARGET_PR_MTE_TCF_SHIFT);
+ ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16,
+ ~env->cp15.gcr_el1);
+ }
return ret;
}
#endif /* AARCH64 */
--
2.25.1
- [PATCH v2 05/17] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE, (continued)
- [PATCH v2 05/17] bsd-user: Tidy VERIFY_READ/VERIFY_WRITE, Richard Henderson, 2020/06/05
- [PATCH v2 06/17] linux-user: Do not use guest_addr_valid for h2g_valid, Richard Henderson, 2020/06/05
- [PATCH v2 08/17] exec: Add support for TARGET_TAGGED_ADDRESSES, Richard Henderson, 2020/06/05
- [PATCH v2 09/17] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE, Richard Henderson, 2020/06/05
- [PATCH v2 07/17] linux-user: Fix guest_addr_valid vs reserved_va, Richard Henderson, 2020/06/05
- [PATCH v2 10/17] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG,
Richard Henderson <=
- [PATCH v2 11/17] linux-user/aarch64: Implement PROT_MTE, Richard Henderson, 2020/06/05
- [PATCH v2 12/17] linux-user/aarch64: Pass syndrome to EXC_*_ABORT, Richard Henderson, 2020/06/05
- [PATCH v2 14/17] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error, Richard Henderson, 2020/06/05
- [PATCH v2 13/17] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault, Richard Henderson, 2020/06/05
- [PATCH v2 16/17] target/arm: Enable MTE for user-only, Richard Henderson, 2020/06/05
- [PATCH v2 15/17] target/arm: Add allocation tag storage for user mode, Richard Henderson, 2020/06/05
- [PATCH v2 17/17] tests/tcg/aarch64: Add mte smoke tests, Richard Henderson, 2020/06/05