Re: [Qemu-devel] [PATCH 10/20] nvic: Add NS alias SCS region

[Peter Maydell]

On Sun, 31 May 2020 at 16:58, Magdy, Mina <Mina_Magdy@mentor.com> wrote:
> I’m currently going through this QEMU patch that related to adding the NS 
> alias for SCS region in ARMv8m cores.

> Why did you assumed that secure accesses to the alias act like NS accesses to 
> the real region registers. I discovered the any register that is accessed 
> through its alias address behaves like accessing it in no secure state 
> (except some cases where current security state is also considered along with 
> the accessed region) ?

I believe that this is the architecturally required behaviour. In the
v8M Arm ARM (DDI0553B.j) rule R_CFPK says "The Secure view of the NS
alias is identical to the Non-secure view of normal addresses unless
otherwise stated".

More generally, the reason that the NS aliases exist is so that
secure software can read and write the NS versions of the registers.
If secure software wants to be able to make changes to bits that are
only writeable in the secure version of the register, it can do
that already via the normal non-alias register.

> My question was come up due to an issue while setting Application
> Interrupt and Reset Control Register (AIRCR). BFHFNMINS , I tried
> to set in secure state  but through the alias register. But as
> investigated from QEMU code, the current security state is set to
> 0 (no secure) but the CPU state is still secure and wasn’t switched
> at this point.

This is what I would expect. The alias is provided so that Secure
code can access the Non-secure version of the AIRCR register. In
the Non-secure version of the AIRCR register, BFHFNMINS is read-only.

Do you find that real hardware behaves differently to QEMU?

thanks
-- PMM