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Re: [PATCH v3 7/7] target/arm: Honor the HCR_EL2.TTLB bit
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 7/7] target/arm: Honor the HCR_EL2.TTLB bit |
Date: |
Tue, 25 Feb 2020 12:01:33 +0000 |
On Tue, 18 Feb 2020 at 19:10, Richard Henderson
<address@hidden> wrote:
>
> This bit traps EL1 access to tlb maintenance insns.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/helper.c | 85 +++++++++++++++++++++++++++++----------------
> 1 file changed, 55 insertions(+), 30 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 21ee9cf7de..87c0cf4a96 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -563,6 +563,16 @@ static CPAccessResult access_tacr(CPUARMState *env,
> const ARMCPRegInfo *ri,
> return CP_ACCESS_OK;
> }
>
> +/* Check for traps from EL1 due to HCR_EL2.TTLB. */
> +static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
> + bool isread)
> +{
> + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + return CP_ACCESS_OK;
> +}
The set of operations this traps differs when ARMv8.4-TLBI is
implemented. It looks like you've applied this access fn to
the wider with-v8.4-TLBI set? (eg TLBI_VMALLE1 is only trapped
with ARMv8.4-TLBI, not without.)
thanks
-- PMM
- Re: [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit, (continued)
- [PATCH v3 2/7] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Richard Henderson, 2020/02/18
- [PATCH v3 4/7] target/arm: Honor the HCR_EL2.TACR bit, Richard Henderson, 2020/02/18
- [PATCH v3 6/7] target/arm: Honor the HCR_EL2.TPU bit, Richard Henderson, 2020/02/18
- [PATCH v3 5/7] target/arm: Honor the HCR_EL2.TPCP bit, Richard Henderson, 2020/02/18
- [PATCH v3 7/7] target/arm: Honor the HCR_EL2.TTLB bit, Richard Henderson, 2020/02/18
- Re: [PATCH v3 7/7] target/arm: Honor the HCR_EL2.TTLB bit,
Peter Maydell <=
- Re: [PATCH v3 0/7] target/arm: Honor more HCR_EL2 traps, Peter Maydell, 2020/02/25