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[PATCH v3 4/7] target/arm: Honor the HCR_EL2.TACR bit
From: |
Richard Henderson |
Subject: |
[PATCH v3 4/7] target/arm: Honor the HCR_EL2.TACR bit |
Date: |
Tue, 18 Feb 2020 11:09:55 -0800 |
This bit traps EL1 access to the auxiliary control registers.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index dc99ee5d18..52b6e68659 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -553,6 +553,16 @@ static CPAccessResult access_tsw(CPUARMState *env, const
ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+/* Check for traps from EL1 due to HCR_EL2.TACR. */
+static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ return CP_ACCESS_OK;
+}
+
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
value)
{
ARMCPU *cpu = env_archcpu(env);
@@ -6911,8 +6921,8 @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
{ .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
+ .access = PL1_RW, .accessfn = access_tacr,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_CONST,
@@ -7668,8 +7678,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo auxcr_reginfo[] = {
{ .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST,
- .resetvalue = cpu->reset_auxcr },
+ .access = PL1_RW, .accessfn = access_tacr,
+ .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr },
{ .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST,
--
2.20.1
- [PATCH v3 0/7] target/arm: Honor more HCR_EL2 traps, Richard Henderson, 2020/02/18
- [PATCH v3 1/7] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn, Richard Henderson, 2020/02/18
- [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit, Richard Henderson, 2020/02/18
- [PATCH v3 2/7] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Richard Henderson, 2020/02/18
- [PATCH v3 4/7] target/arm: Honor the HCR_EL2.TACR bit,
Richard Henderson <=
- [PATCH v3 6/7] target/arm: Honor the HCR_EL2.TPU bit, Richard Henderson, 2020/02/18
- [PATCH v3 5/7] target/arm: Honor the HCR_EL2.TPCP bit, Richard Henderson, 2020/02/18
- [PATCH v3 7/7] target/arm: Honor the HCR_EL2.TTLB bit, Richard Henderson, 2020/02/18
- Re: [PATCH v3 0/7] target/arm: Honor more HCR_EL2 traps, Peter Maydell, 2020/02/25