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Re: [PATCH 07/21] aspeed/timer: Add support for IRQ status register on t
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From: |
Joel Stanley |
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Subject: |
Re: [PATCH 07/21] aspeed/timer: Add support for IRQ status register on the AST2600 |
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Date: |
Fri, 20 Sep 2019 04:43:30 +0000 |
On Thu, 19 Sep 2019 at 05:51, Cédric Le Goater <address@hidden> wrote:
>
> The AST2600 timer replaces control register 2 with a interrupt status
> register. It is set by hardware when an IRQ occurs and cleared by
> software.
>
> Modify the vmstate version to take into account the new fields.
>
> Based on previous work from Joel Stanley.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
- [Qemu-arm] [PATCH 03/21] hw: aspeed_scu: Add AST2600 support, (continued)
[Qemu-arm] [PATCH 04/21] aspeed/timer: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 05/21] aspeed/timer: Add support for control register 3, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 06/21] aspeed/timer: Add AST2600 support, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 07/21] aspeed/timer: Add support for IRQ status register on the AST2600, Cédric Le Goater, 2019/09/19
- Re: [PATCH 07/21] aspeed/timer: Add support for IRQ status register on the AST2600,
Joel Stanley <=
[Qemu-arm] [PATCH 08/21] aspeed/sdmc: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 09/21] aspeed/sdmc: Add AST2600 support, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 10/21] watchdog/aspeed: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 11/21] hw: wdt_aspeed: Add AST2600 support, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 12/21] aspeed/smc: Add AST2600 support, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 13/21] hw/gpio: Add in AST2600 specific implementation, Cédric Le Goater, 2019/09/19