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Re: [PATCH 01/21] aspeed/wdt: Check correct register for clock source
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From: |
Joel Stanley |
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Subject: |
Re: [PATCH 01/21] aspeed/wdt: Check correct register for clock source |
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Date: |
Fri, 20 Sep 2019 04:41:11 +0000 |
On Thu, 19 Sep 2019 at 05:50, Cédric Le Goater <address@hidden> wrote:
>
> From: Amithash Prasad <address@hidden>
>
> When WDT_RESTART is written, the data is not the contents
> of the WDT_CTRL register. Hence ensure we are looking at
> WDT_CTRL to check if bit WDT_CTRL_1MHZ_CLK is set or not.
>
> Signed-off-by: Amithash Prasad <address@hidden>
> [clg: improved Suject prefix ]
> Signed-off-by: Cédric Le Goater <address@hidden>
A patch from the Open Source Firmware Conference! Thanks Amithash.
Reviewed-by: Joel Stanley <address@hidden>
> ---
> hw/watchdog/wdt_aspeed.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
> index 9b932134172c..f710036535da 100644
> --- a/hw/watchdog/wdt_aspeed.c
> +++ b/hw/watchdog/wdt_aspeed.c
> @@ -140,7 +140,7 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset,
> uint64_t data,
> case WDT_RESTART:
> if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
> s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
> - aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
> + aspeed_wdt_reload(s, !(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK));
> }
> break;
> case WDT_CTRL:
> --
> 2.21.0
>
[Qemu-arm] [PATCH 04/21] aspeed/timer: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 05/21] aspeed/timer: Add support for control register 3, Cédric Le Goater, 2019/09/19
[Qemu-arm] [PATCH 06/21] aspeed/timer: Add AST2600 support, Cédric Le Goater, 2019/09/19