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Re: [Qemu-arm] [PATCH v2 21/68] target/arm: Convert Synchronization prim
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH v2 21/68] target/arm: Convert Synchronization primitives |
Date: |
Tue, 27 Aug 2019 11:44:24 +0100 |
On Mon, 19 Aug 2019 at 22:38, Richard Henderson
<address@hidden> wrote:
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate.c | 560 ++++++++++++++++++++++-------------------
> target/arm/a32.decode | 48 ++++
> target/arm/t32.decode | 46 ++++
> 3 files changed, 396 insertions(+), 258 deletions(-)
> +static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a)
> +{
> + if (!ENABLE_ARCH_6K || (a->rt & 1)) {
> + return false;
> + }
> + a->rt2 = a->rt + 1;
> + return op_strex(s, a, MO_64, false);
> +}
I've just noticed that there's a bug in these checks -- the
M-profile CPUs don't have the V6K feature, but they should
still have STREXB/STREXH/STREXD, and with this test they'll
incorrectly UNDEF them.
thanks
-- PMM
- Re: [Qemu-arm] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW, (continued)
[Qemu-arm] [PATCH v2 22/68] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/08/19
[Qemu-arm] [PATCH v2 21/68] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/08/19
[Qemu-arm] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/08/19
[Qemu-arm] [PATCH v2 20/68] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/08/19
[Qemu-arm] [PATCH v2 23/68] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/08/19