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[Qemu-arm] [PATCH v4 08/21] target/arm: Allow EL change hooks to do IO
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v4 08/21] target/arm: Allow EL change hooks to do IO |
Date: |
Tue, 17 Apr 2018 16:37:52 -0400 |
During code generation, surround CPSR writes and exception returns which
call the EL change hooks with gen_io_start/end. The immediate need is
for the PMU to access the clock and icount during EL change to support
mode filtering.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/translate-a64.c | 6 ++++++
target/arm/translate.c | 12 ++++++++++++
2 files changed, 18 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c913292..bff4e13 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1930,7 +1930,13 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
unallocated_encoding(s);
return;
}
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_exception_return(cpu_env);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
return;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index db1ce65..9bc2ce1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4548,7 +4548,13 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc,
TCGv_i32 cpsr)
* appropriately depending on the new Thumb bit, so it must
* be called after storing the new PC.
*/
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_cpsr_write_eret(cpu_env, cpsr);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
tcg_temp_free_i32(cpsr);
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
@@ -9843,7 +9849,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
if (exc_return) {
/* Restore CPSR from SPSR. */
tmp = load_cpu_field(spsr);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
gen_helper_cpsr_write_eret(cpu_env, tmp);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ }
tcg_temp_free_i32(tmp);
/* Must exit loop to check un-masked IRQs */
s->base.is_jmp = DISAS_EXIT;
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v4 00/21] More fully implement ARM PMUv3, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 01/21] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 02/21] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 05/21] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 04/21] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 06/21] target/arm: Support multiple EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 07/21] target/arm: Add pre-EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 08/21] target/arm: Allow EL change hooks to do IO,
Aaron Lindsay <=
- [Qemu-arm] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 11/21] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 10/21] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 14/21] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 18/21] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 13/21] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 17/21] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 15/21] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 16/21] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/04/17