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[Qemu-arm] [PATCH v4 04/21] target/arm: Mask PMU register writes based o
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v4 04/21] target/arm: Mask PMU register writes based on PMCR_EL0.N |
Date: |
Tue, 17 Apr 2018 16:37:48 -0400 |
This is in preparation for enabling counters other than PMCCNTR
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 31 ++++++++++++++++++++++---------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f6269a2..8bec07e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -52,11 +52,6 @@ typedef struct V8M_SAttributes {
static void v8m_security_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
V8M_SAttributes *sattrs);
-
-/* Definitions for the PMCCNTR and PMCR registers */
-#define PMCRD 0x8
-#define PMCRC 0x4
-#define PMCRE 0x1
#endif
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
@@ -906,6 +901,24 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
REGINFO_SENTINEL
};
+/* Definitions for the PMU registers */
+#define PMCRN_MASK 0xf800
+#define PMCRN_SHIFT 11
+#define PMCRD 0x8
+#define PMCRC 0x4
+#define PMCRE 0x1
+
+static inline uint32_t pmu_num_counters(CPUARMState *env)
+{
+ return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
+}
+
+/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
+static inline uint64_t pmu_counter_mask(CPUARMState *env)
+{
+ return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
+}
+
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
@@ -1119,14 +1132,14 @@ static void pmccfiltr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= pmu_counter_mask(env);
env->cp15.c9_pmcnten |= value;
}
static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= pmu_counter_mask(env);
env->cp15.c9_pmcnten &= ~value;
}
@@ -1174,14 +1187,14 @@ static void pmintenset_write(CPUARMState *env, const
ARMCPRegInfo *ri,
uint64_t value)
{
/* We have no event counters so only the C bit can be changed */
- value &= (1 << 31);
+ value &= pmu_counter_mask(env);
env->cp15.c9_pminten |= value;
}
static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= pmu_counter_mask(env);
env->cp15.c9_pminten &= ~value;
}
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH v4 00/21] More fully implement ARM PMUv3, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 01/21] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 02/21] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 05/21] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 04/21] target/arm: Mask PMU register writes based on PMCR_EL0.N,
Aaron Lindsay <=
- [Qemu-arm] [PATCH v4 03/21] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 06/21] target/arm: Support multiple EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 07/21] target/arm: Add pre-EL change hooks, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 08/21] target/arm: Allow EL change hooks to do IO, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 09/21] target/arm: Fix bitmask for PMCCFILTR writes, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 11/21] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 12/21] target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide, Aaron Lindsay, 2018/04/17
- [Qemu-arm] [PATCH v4 10/21] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/04/17