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[Qemu-arm] [PATCH 09/13] target/arm: Add array for supported PMU events,
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01] |
Date: |
Wed, 19 Apr 2017 13:41:20 -0400 |
This commit doesn't add any supported events, but provides the framework
for adding them. We store the pm_event structs in a simple array, and
provide the mapping from the event numbers to array indexes in
the supported_event_map array.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/cpu.c | 4 ++++
target/arm/cpu.h | 10 ++++++++++
target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 44c965c..d61ea12 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -788,6 +788,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
if (!cpu->has_pmu) {
cpu->has_pmu = false;
unset_feature(env, ARM_FEATURE_PMU);
+ } else {
+ uint64_t pmceid = get_pmceid(&cpu->env);
+ cpu->pmceid0 = pmceid & 0xffffffff;
+ cpu->pmceid1 = (pmceid >> 32) & 0xffffffff;
}
if (!arm_feature(env, ARM_FEATURE_EL2)) {
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f3524f6..57ca684 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -780,6 +780,16 @@ void pmccntr_sync(CPUARMState *env);
*/
void pmu_sync(CPUARMState *env);
+/*
+ * get_pmceid
+ * @env: CPUARMState
+ *
+ * Return the PMCEID[01] register values corresponding to the counters which
+ * are supported given the current configuration (0 is low 32, 1 is high 32
+ * bits)
+ */
+uint64_t get_pmceid(CPUARMState *env);
+
/* SCTLR bit meanings. Several bits have been reused in newer
* versions of the architecture; in that case we define constants
* for both old and new bit meanings. Code which tests against those
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5d07f72..a0ae201 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -891,6 +891,43 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
#define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) - 1))
+typedef struct pm_event {
+ uint16_t number; /* PMEVTYPER.evtCount is 10 bits wide */
+ /* If the event is supported on this CPU (used to generate PMCEID[01]) */
+ bool (*supported)(CPUARMState *);
+ /* Retrieve the current count of the underlying event. The programmed
+ * counters hold a difference from the return value from this function */
+ uint64_t (*get_count)(CPUARMState *);
+} pm_event;
+
+#define SUPPORTED_EVENT_SENTINEL UINT16_MAX
+static const pm_event pm_events[] = {
+ { .number = SUPPORTED_EVENT_SENTINEL }
+};
+static uint16_t supported_event_map[0x3f];
+
+/*
+ * Called upon initialization to build PMCEID0 (low 32 bits) and PMCEID1 (high
+ * 32). We also use it to build a map of ARM event numbers to indices in
+ * our pm_events array.
+ */
+uint64_t get_pmceid(CPUARMState *env)
+{
+ uint64_t pmceid = 0;
+ unsigned int i = 0;
+ while (pm_events[i].number != SUPPORTED_EVENT_SENTINEL) {
+ const pm_event *cnt = &pm_events[i];
+ if (cnt->number < 0x3f && cnt->supported(env)) {
+ pmceid |= (1 << cnt->number);
+ supported_event_map[cnt->number] = i;
+ } else {
+ supported_event_map[cnt->number] = SUPPORTED_EVENT_SENTINEL;
+ }
+ i++;
+ }
+ return pmceid;
+}
+
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH 00/13] More fully implement ARM PMUv3, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0], Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01],
Aaron Lindsay <=
- [Qemu-arm] [PATCH 07/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 13/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2017/04/19
- Re: [Qemu-arm] [Qemu-devel] [PATCH 00/13] More fully implement ARM PMUv3, no-reply, 2017/04/19