[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0]
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0] |
Date: |
Wed, 19 Apr 2017 13:41:12 -0400 |
A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01]
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/cpu.c | 2 +-
target/arm/cpu64.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 04b062c..921b028 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1342,7 +1342,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011;
cpu->id_dfr0 = 0x02010555;
- cpu->pmceid0 = 0x0000000;
+ cpu->pmceid0 = 0x00000000;
cpu->pmceid1 = 0x00000000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10201105;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 670c07a..7b1642e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -198,6 +198,8 @@ static void aarch64_a53_initfn(Object *obj)
cpu->id_isar5 = 0x00011121;
cpu->id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106;
+ cpu->pmceid0 = 0x00000000;
+ cpu->pmceid1 = 0x00000000;
cpu->id_aa64isar0 = 0x00011120;
cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
cpu->dbgdidr = 0x3516d000;
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-arm] [PATCH 00/13] More fully implement ARM PMUv3, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0],
Aaron Lindsay <=
- [Qemu-arm] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 07/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2017/04/19
- [Qemu-arm] [PATCH 13/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2017/04/19